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psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53413 rev. *o revised june 18, 2012 general description with its unique array of configurable blocks, psoc ? 3 is a true system level solution prov iding microcontroller unit (mcu), memory, analog, and digital peripheral functions in a single chip. the cy 8c36 family offers a modern me thod of signal acquisition, sign al processing, and control with high accuracy, high bandwidth, and high flexibility. analog capability spans the range from thermo couples (near dc voltages) to ultrasonic signals. the cy8c36 family can handle dozens of data acquisition channels and analog inputs on every general-purpose i nput/output (gpio) pin. the cy8c36 family is also a high-perf ormance configurable digital system with so me part numbers including interfaces such as usb, multi-master inte r-integrated circuit (i 2 c), and controller area network (can). in addition to communication interfaces, the cy8c36 family has an ea sy to configure logic array, flexible routing to all i/o pins, and current dac a high-performance single cycle 8051 microprocessor core. yo u can easily create system-lev el designs using a rich library of prebuilt components and boolean primitives using psoc creator?, a hierarch ical schematic design entry tool. the cy8c 36 family provides unparalleled opportunities for analog and digita l bill of materials integration while easily accommodating last minute design changes through simple firmware updates. features ? single cycle 8051 cpu core ? dc to 67 mhz operation ? multiply and divide instructions ? flash program memory, up to 64 kb, 100,000 write cycles, 20 years retention, and multiple security features ? 512-byte flash cache ? up to 8-kb flash error correcting code (ecc) or configuration storage ? up to 8 kb sram ? up to 2 kb electrically erasable programmable read-only memory (eeprom), 1 m cycles, and 20 years retention ? 24-channel direct memory a ccess (dma) with multilayer ahb [1] bus access ? programmable chained descriptors and priorities ? high bandwidth 32-bit transfer support ? low voltage, ultra low-power ? wide operating voltage range: 0.5 v to 5.5 v ? high efficiency boost regulator from 0.5-v input through 1.8-v to 5.0-v output ? 0.8 ma at 3 mhz, 1.2 ma at 6 mhz, 6.6 ma at 48 mhz ? low-power modes including: ? 1-a sleep mode with real-time clock (rtc) and low-voltage detect (lvd) interrupt ? 200-na hibernate mode with ram retention ? versatile i/o system ? 28 to 72 i/o (62 gpios, eight special input/outputs (sio), two usbios [2] ? any gpio to any digital or analog peripheral routability ? lcd direct drive from any gpio, up to 46 16 segments [2] ? capsense ? support from any gpio [3] ? 1.2-v to 5.5-v i/o interface voltages, up to four domains ? maskable, independent interrupt request (irq) on any pin or port ? schmitt-trigger transistor-t ransistor logic (ttl) inputs ? all gpio configurable as open drain high/low, pull-up/pull-down, high z, or strong output ? configurable gpio pin state at power-on reset (por) ? 25 ma sink on sio ? digital peripherals ? 20 to 24 programmable logic devices (pld) based universal digital blocks (udb) ? full can 2.0b 16-receive (rx), 8-transmit (tx) buffers [2] ? full-speed (fs) usb 2.0 12 mbps using internal oscillator [2] ? up to four 16-bit configurable timer, counter, and pwm blocks ? 67-mhz, 24-bit fixed point digital filter block (dfb) to implement finite impulse response (fir) and infinite impulse response (iir) filters ? library of standard peripherals ? 8-, 16-, 24-, and 32-bit timers, counters, and pwms ? serial peripheral interface (spi), universal asynchronous transmitter receiver (uart), i 2 c ? many others available in catalog ? library of advanced peripherals ? cyclic redundancy check (crc) ? pseudo random sequence (prs) generator ? local interconnect network (lin) bus 2.0 ? quadrature decoder ? analog peripherals (1.71 v ? v dda ? 5.5 v) ? 1.024 v 0.1% internal voltage reference across ?40 c to +85 c ? configurable delta-sigma adc with 8- to12-bit resolution ? programmable gain stage: 0.25 to 16 ? 12-bit mode, 192-ksps, 66-db signal to noise and distortion ratio (sinad), 1-bit inl/dnl ? up to four 8-bit, 8-msps idacs or 1-msps vdacs ? four comparators with 95-ns response time ? up to four uncommitted opamps with 25 ma drive capability ? up to four configur able multifunction an alog blocks. example configurations are programmable gain amplifier (pga), transimpedance amplifier (tia), mixer, and sample and hold ? capsense support ? programming, debug, and trace ? jtag (4-wire), serial wire debug (swd) (2-wire), and single wire viewer (swv) interfaces ? eight address and one data breakpoint ? 4-kb instruction trace buffer ? bootloader programming supportable through i 2 c, spi, uart, usb, and other interfaces ? precision, programmable clocking ? 3- to 62-mhz internal oscillator over full temperature and voltage range ? 4- to 25-mhz crystal oscillat or for crystal ppm accuracy ? internal pll clock generation up to 67 mhz ? 32.768 khz watch crystal oscillator ? low-power internal oscillator at 1, 33, and 100 khz ? temperature and packaging ? ?40 c to +85 c degrees industrial temperature ? 48-pin ssop, 48-pin qfn, 68-pin qfn, and 100-pin tqfp package options notes 1. ahb ? amba (advanced microcontroller bus architecture) high-performance bus, an arm data transfer bus 2. this feature on select devices only. see ordering information on page 116 for details. 3. gpios with opamp outputs are not recommended for use with capsense.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 2 of 131 contents 1. architectural overview ................................................. 3 2. pinouts ........................................................................... 5 3. pin descriptions .......................................................... 10 4. cpu ............................................................................... 11 4.1 8051 cpu .............................................................11 4.2 addressing modes ................................................12 4.3 instruction set ......................................................12 4.4 dma and phub ...................................................16 4.5 interrupt controller ...............................................18 5. memory ......................................................................... 21 5.1 static ram ...........................................................21 5.2 flash program memory ........................................21 5.3 flash security .......................................................21 5.4 eeprom ...... ............... ........... ........... ........... ........22 5.5 nonvolatile latches (nvls) ..................................22 5.6 external memory interface ...................................23 5.7 memory map ........................................................23 6. system integration ...................................................... 26 6.1 clocking system ...................................................26 6.2 power system ......................................................29 6.3 reset ....................................................................33 6.4 i/o system and routing .......................................34 7. digital subsystem ....................................................... 41 7.1 example peripherals ............................................41 7.2 universal digital block ..........................................44 7.3 udb array description ..... ....................................47 7.4 dsi routing interface descr iption ........................47 7.5 can ......................................................................49 7.6 usb ......................................................................51 7.7 timers, counters, and pwms ..............................51 7.8 i 2 c ........................................................................52 7.9 digital filter block .................................................53 8. analog subsystem ...................................................... 53 8.1 analog routing .....................................................54 8.2 delta-sigma adc ..................................................56 8.3 comparators .........................................................57 8.4 opamps ................................................................58 8.5 programmable sc/ct bloc ks ..............................58 8.6 lcd direct drive ..................................................59 8.7 capsense .............................................................60 8.8 temp sensor ........................................................60 8.9 dac ......................................................................60 8.10 up/down mixer ...................................................61 8.11 sample and hold ........... .....................................61 9. programming, debug interfaces, resources ............ 62 9.1 jtag interface .....................................................62 9.2 serial wire debug interface .................................64 9.3 debug features ....................................................65 9.4 trace features .....................................................65 9.5 single wire viewer interf ace ................................65 9.6 programming features .........................................65 9.7 device security ............ ........................................65 10. development support ............................................... 66 10.1 documentation .............. .....................................66 10.2 online .................................................................66 10.3 tools ...................................................................66 11. electrical specifications ........................................... 67 11.1 absolute maximum rating s ................................67 11.2 device level specificatio ns ................................68 11.3 power regulators ...............................................72 11.4 inputs and outputs .............................................75 11.5 analog peripherals ........ .....................................82 11.6 digital peripherals ..............................................99 11.7 memory ............................................................103 11.8 psoc system resources .................................109 11.9 clocking ......................... ...................................112 12. ordering information ............................................... 116 12.1 part numbering conventio ns ...........................117 13. packaging .... .............. .............. ............... .............. .... 118 14. acronyms ................................................................. 122 15. reference documents .......... ................................... 123 16. document conventions .......................................... 124 16.1 units of measure ..............................................124 17. revision history ...................................................... 125 18. sales, solutions, and legal information ............... 131
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 3 of 131 1. architectural overview introducing the cy8c36 family of ultra low-po wer, flash programmable system-on-chip (psoc ? ) devices, part of a scalable 8-bit psoc 3 and 32-bit psoc 5 platform. the cy8c36 family provides configurable blocks of analog, digital, and interconnect circuitry around a cpu subsystem. the comb ination of a cpu with a flexible analog subsystem, digital sub system, routing, and i/o enables a high level of integration in a wide variety of consumer, industrial, and medical applications. figure 1-1. simplified block diagram figure 1-1 illustrates the major components of the cy8c36 family. they are: ? 8051 cpu subsystem ? nonvolatile subsystem ? programming, debug, and test subsystem ? inputs and outputs ? clocking ? power ? digital subsystem ? analog subsystem psoc?s digital subsystem pr ovides half of its unique configurability. it connects a digital signal from any peripheral to any pin through the digital system interconnect (dsi). it also provides functional flexibility through an array of small, fast, low-power udbs. psoc creator provides a library of prebuilt and tested standard digital peripher als (uart, spi, lin, prs, crc, timer, counter, pwm, and, or, and so on) that are mapped to the udb array. you can also easily create a digital circuit using boolean primitives by means of graphical design entry. each udb contains programmable array logic (pal)/programmable logic device (pld) functionality, together with a small state machine engine to support a wide variety of peripherals. digital filter block analog system lcd direct drive capsense temperature sensor 4 x opamp + - adc 4 x dac del sig adc 4 x sc/ ct blocks (tia, pga, mixer etc) 4 x cmp + - can 2.0 i2c master/ slave universal digital block array (24 x udb) 4 x timer counter pwm fs usb 2.0 system wide resources digital system program debug & trace boundary scan program & debug 8051 or cortex m3 cpu interrupt controller phub dma sram flash eeprom emif cpu system memory system system bus digital interconnect analog interconnect 1.71 to 5.5 v 0. 5 to 5.5v ( optional) 4 to 25 mhz ( optional ) xtal osc 32. 768 khz ( optional ) rtc timer imo clock tree wdt and wake ilo clocking system 1.8 v ldo smp por and lvd sleep power power management system usb phy 3 per opamp gpios gpios gpios gpios gpios gpios sio gpios sios udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb uart logic 12- bit pwm i2c slave 8- bit spi 12- bit spi logic 8- bit timer 16- bit prs udb 8- bit timer quadrature decoder 16- bit pwm sequencer usage example for udb udb udb udb udb udb udb udb udb 22 ?
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 4 of 131 in addition to the flexibility of the udb array, psoc also provides configurable digital blocks targeted at specific functions. for the cy8c36 family these blocks can include four 16-bit timers, counters, and pwm blocks; i 2 c slave, master, and multi-master; fs usb; and full can 2.0b. for more details on the peripherals see the ?example peripherals? section on page 41 of this data sheet. for information on udbs, dsi, and other digital blocks, see the ?digital subsystem? section on page 41 of this data sheet. psoc?s analog subsystem is the second half of its unique configurability. all analog performance is based on a highly accurate absolute voltage reference with less than 0.1-percent error over temperature and voltage. the configurable analog subsystem includes: ? analog muxes ? comparators ? voltage references ? adc ? dacs ? dfb all gpio pins can route analog signals into and out of the device using the internal analog bus. this allows the device to interface up to 62 discrete analog signals. the heart of the analog subsystem is a fast, accurate, configurable delta-sigma adc with these features: ? less than 100 v offset ? a gain error of 0.2 percent ? inl less than 1 lsb ? dnl less than 1 lsb ? sinad better than 66 db this converter addresses a wide variety of precision analog applications, including some of the most demanding sensors. the output of the adc can opt ionally feed the programmable dfb through the dma without cpu intervention. you can configure the dfb to perform iir and fir digital filters and several user-defined custom functions. the dfb can implement filters with up to 64 taps. it can perform a 48-bit multiply-accumulate (mac) operation in one clock cycle. four high-speed voltage or curr ent dacs support 8-bit output signals at an update rate of up to 8 msps. they can be routed out of any gpio pin. you can create higher resolution voltage pwm dac outputs using the udb array. this can be used to create a pwm dac of up to 10 bits, at up to 48 khz. the digital dacs in each udb support pwm, prs, or delta-sigma algorithms with programmable widths. in addition to the adc, dacs, and dfb, the ana log subsystem provides multiple: ? uncommitted opamps ? configurable switched capacitor/continuous time (sc/ct) blocks. these support: ? transimpedance amplifiers ? programmable gain amplifiers ? mixers ? other similar analog components see the ?analog subsystem? section on page 53 of this data sheet for more details. psoc?s 8051 cpu subsystem is built around a single-cycle pipelined 8051 8-bit processor running at up to 67 mhz. the cpu subsystem includes a prog rammable nested vector interrupt controller, dma controller, and ram. psoc?s nested vector interrupt controller provides low latency by allowing the cpu to vector directly to the firs t address of the interrupt service routine, bypassing the jump instruction required by other architectures. the dma controller enables peripherals to exchange data without cpu involvement. this allows the cpu to run slower (saving power) or use those cpu cycles to improve the performance of firmware al gorithms. the si ngle cycle 8051 cpu runs ten times faster than a standard 8051 processor. the processor speed itself is configurable, allowing you to tune active power consumption for specific applications. psoc?s nonvolatile subsystem consis ts of flash, byte-writeable eeprom, and nonvolatile configuration options. it provides up to 64 kb of on-chip flash. the cpu can reprogram individual blocks of flash, enabling bootl oaders. you can enable an ecc for high reliability applications. a po werful and flexible protection model secures the user's sensitive information, allowing selective memory block locking fo r read and write protection. up to 2 kb of byte-writeable eeprom is available on-chip to store application data. additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. this allows settings to activate immediately after por. the three types of psoc i/o are ex tremely flexible. all i/os have many drive modes that are set at por. psoc also provides up to four i/o voltage domains thro ugh the vddio pins. every gpio has analog i/o, lcd drive [4] , capsense [5] , flexible interrupt generation, slew rate control, and digital i/o capability. the sios on psoc allow v oh to be set independently of v ddio when used as outputs. when sios are in input mode they are high impedance. this is true even w hen the device is not powered or when the pin voltage goes above the supply voltage. this makes the sio ideally suited for use on an i 2 c bus where the psoc may not be powered when other devices on the bus are. the sio pins also have high current sink capability for applications such as led drives. the programmable input threshold feature of the sio can be used to make the sio function as a general purpose analog comparator. for devices with fs usb the usb physical interface is also provided (usbio). when not using usb these pins may also be used for limited digital functionality and device programming. all of the features of the psoc i/os are covered in detail in the ?i/o system and routing? section on page 34 of this data sheet. the psoc device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. the internal main oscillator (i mo) is the clock base for the system, and has 1-percent accura cy at 3 mhz. the imo can be configured to run from 3 mhz up to 62 mhz. multiple clock derivatives can be generated from the main clock frequency to meet application needs. the device provides a pll to generate clock frequencies up to 67 mhz from the imo, external crystal, or external reference clock. it also contains a separate, very low-power internal low speed oscillator (ilo) for the sleep and watchdog timers. a 32.768-khz external watch crystal is also supported for use in rt c applications. the cl ocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 5 of 131 the cy8c36 family supports a wid e supply operating range from 1.71 to 5.5 v. this allows operation from regulated supplies such as 1.8 5%, 2.5 v 10%, 3.3 v 10%, or 5.0 v 10%, or directly from a wide range of battery type s. in addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 v. this enables the device to be powered directly from a single battery or solar cell. in addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-v supply for lcd glass drive. the boost?s output is available on the v boost pin, allowing other devices in the application to be powered from the psoc. psoc supports a wide range of low-power modes. these include a 200-na hibernate mode with ram retention and a 1-a sleep mode with rtc. in the second mode the optional 32.768-khz watch crystal runs continuously and maintains an accurate rtc. power to all major functional bl ocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. this allows low-power background processing when some peripherals are not in use. this, in turn, provides a total device current of only 1.2 ma when the cpu is running at 6 mhz, or 0.8 ma running at 3 mhz. the details of the psoc power modes are covered in the ?power system? section on page 29 of this data sheet. psoc uses jtag (4-wire) or swd (2-wire) interfaces for programming, debug, and test. the 1-wire swv may also be used for ?printf? style debugging. by combining swd and swv, you can implement a full debugging interface with just three pins. using these standard interfaces enables you to debug or program the psoc with a variety of hardware solutions from cypress or third party vendors. psoc supports on-chip break points and 4-kb instruction and data race memory for debug. details of the programming, test, and debugging interfaces are discussed in the ?programming, debug interfaces, resources? section on page 62 of this data sheet. 2. pinouts each vddio pin powers a specific set of i/o pins. (the usbios are powered from vddd.) using the vddio pins, a single psoc can support multiple voltage levels, reducing the need for off-chip level shifters. the black lines drawn on the pinout diagrams in figure 2-3 through figure 2-6 show the pins that are powered by each vddio. each vddio may source up to 100 ma total to its associated i/o pins, as shown in figure 2-1 . figure 2-1. vddio current limit conversely, for the 100-pin and 68-pin devices, the set of i/o pins associated with any vddio ma y sink up to 100 ma total, as shown in figure 2-2 . figure 2-2. i/o pins current limit for the 48-pin devices, the set of i/o pins associated with vddio0 plus vddio2 may sink up to 100 ma total. the set of i/o pins associated with vddio1 plus vddio3 may sink up to a total of 100 ma. psoc v ddio x i ddio x = 100 ma i/o pins psoc v ddio x ipins = 100 ma i/o pins v ssd notes 4. this feature on select devices only. see ordering information on page 116 for details. 5. gpios with opamp outputs are not recommended for use with capsense.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 6 of 131 figure 2-3. 48-pin ssop part pinout figure 2-4. 48-pin qfn part pinout [7] ssop vssa (sio) p12[3] 247 vcca (opamp2out, gpio) p0[0] 346 p15[3] (gpio, khz xtal: xi) (opamp0out, gpio) p0[1] 445 p12[0] (sio, i2c1: scl) vddio0 742 p12[1] (sio, i2c1: sda) 643 (opamp0-/extref0, gpio) p0[3] p15[1] (gpio, mhz xtal: xi) (opamp2-, gpio) p0[5] 940 p15[0] (gpio, mhz xtal: xo) (idac0, gpio) p0[6] 10 39 vccd (idac2, gpio) p0[7] 11 38 vssd vccd 12 37 vddd vssd 13 36 p15[7] (usbio, d-, swdck) vddd 14 35 p15[6] (usbio, d+, swdio) (gpio) p2[3] 15 34 p1[7] (gpio) (gpio) p2[4] 16 33 p1[6] (gpio) vddio2 17 32 vddio1 (gpio) p2[5] 18 31 p1[5] (gpio, ntrst) (gpio) p2[6] 19 30 p1[4] (gpio, tdi) (gpio) p2[7] 20 29 p1[3] (gpio, tdo, swv) vssb 21 28 ind 22 27 p1[1] (gpio, tck, swdck) vboost 23 26 p1[0] (gpio, tms, swdio) vbat 24 25 vdda (sio) p12[2] 148 vddio3 (opamp2+, gpio) p0[4] 841 p15[2] (gpio, khz xtal: xo) (opamp0+, gpio) p0[2] 544 lines show vddio to i/o supply association p1[2] (gpio, configurable xres) [6] [6] qfn (top view) vddio2 vddio0 10 11 12 vssb ind vb vbat 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 vddio1 (gpio) p1[6] vddd vssd vccd (gpio, mhz xtal: xo) p15[0] vddio3 vccd p2[5] (gpio) (gpio) p1[7] (gpio, mhz xtal: xi) p15[1] vcca vssa vdda vddd vssd p12[2] (sio) p12[3] (sio) p0[0] (opamp2out, gpio) p0[1] (opamp0out, gpio) p0[2] (opamp0+, gpio) p0[3] (opamp0-/extref0, gpio) p0[4] (opamp2+, gpio) p0[5] (opamp2-, gpio) p0[6] (idac0, gpio) p0[7] (idac2, gpio) p2[3] (gpio) p2[4] (gpio) (gpio) p2[6] (gpio) p2[7] (gpio, ntrst) p1[5] (gpio, tdi) p1[4] (gpio, tdo, swv) p1[3] (gpio, tck, swdck) p1[1] (gpio, tms, swdio) p1[0] (gpio, configurable xres) p1[2] (sio, i2c1: scl) p12[0] p12[1] (sio, i2c1: sda) p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) (usbio, d-, swdck) p15[7] (usbio, d+, swdio) p15[6] lines show vddio to i/o supply association [6] [6] notes 6. pins are do not use (dnu) on devices without usb. the pin must be left floating. 7. the center pad on the qfn package should be connected to digita l ground (vssd) for best mechanical, thermal, and electrical p erformance. if not connected to ground, it should be electrically floated and not connected to any other signal.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 7 of 131 figure 2-5. 68-pin qfn part pinout [10] notes 8. pins are do not use (dnu) on devices with out usb. the pin must be left floating. 9. this feature on select devices only. see ordering information on page 116 for details. 10. the center pad on the qfn package should be connected to digital ground (vssd) for best mechanical, thermal, and electrical performance. if not connected to ground, it should be electrically floate d and not connected to any other signal. (gpio) p2[6] (gpio) p2[7] (i2c0: scl, sio) p12[4] (i2c0: sda, sio) p12[5] vssb ind vboost vbat vssd xres (tms, swdio, gpio) p1[0] (tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] (tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] (ntrst, gpio) p1[5] vddio1 (gpio) p1[6] vccd (opamp3+, gpio) p3[3] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (idac1, gpio) p3[0] (idac3, gpio) p3[1] (opamp3-/extref1, gpio) p3[2] (opamp1-, gpio) p3[4] (opamp1+, gpio) p3[5] p0[3] (gpio, opamp0-/extref0) p0[2] (gpio,opamp0+) p0[1] (gpio, opamp0out) p0[0] (gpio, opamp2out) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) p12[1] (sio, i2c1: sda) p12[0] (sio, 12c1: scl) p3[7] (gpio, opamp3out) p3[6] (gpio, opamp1out) vddio3 p2[5] (gpio) vddio2 p2[4] (gpio) p2[3] (gpio) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpoi) p15[4] (gpio) vddd vssd vccd p0[7] (gpio, idac2) p0[6] (gpio, idac0) p0[5] (gpio, opamp2-) p0[4] (gpio, opamp2+) vddio0 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) lines show vddio to i/o supply association [9] [9] [9] [9] [9] [8] [8] [9]
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 8 of 131 figure 2-6. 100-pin tqfp part pinout figure 2-7 and figure 2-8 on page 10 show an example schematic and an example pcb layout, for the 100-pin tqfp part, for optimal analog performance on a two-layer board. ? the two pins labeled vddd must be connected together. ? the two pins labeled vccd must be connected together, with capacitance added, as shown in figure 2-7 and power system on page 29. the trace between the two vccd pins should be as short as possible. ? the two pins labeled vssd must be connected together. for information on circuit board layout issues for mixed signals, refer to the application note an57821 - mixed signal circuit board layout considerations for psoc? 3 and psoc 5. tqfp (gpio) p2[5] (gpio) p2[6] (gpio) p2[7] (i2c0: scl, sio) p12[4] (i2c0: sda, sio) p12[5] (gpio) p6[4] (gpio) p6[5] (gpio) p6[6] (gpio) p6[7] vssb ind vboost vbat vssd xres (gpio) p5[0] (gpio) p5[1] (gpio) p5[2] (gpio) p5[3] (tms, swdio, gpio) p1[0] (tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] (tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] (ntrst, gpio) p1[5] vddio1 (gpio) p5[7] nc (opamp3-/extref1, gpio) p3[2] (gpio) p1[6] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (gpio) p5[4] (gpio) p5[5] (gpio) p5[6] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd vccd nc (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (idac1, gpio) p3[0] (idac3, gpio) p3[1] (opamp3+, gpio) p3[3] (opamp1-, gpio) p3[4] (opamp1+, gpio) p3[5] vddio3 vddio0 p0[3] (gpio, opamp0-/extref0) p0[2] (gpio, opamp0+) p0[1] (gpio, opamp0out) p0[0] (gpio, opamp2out) p4[1] (gpio) p4[0] (gpio) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca nc nc nc nc nc nc p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) p12[1] (sio, i2c1: sda) p12[0] (sio, i2c1: scl) p3[7] (gpio, opamp3out) p3[6] (gpio, opamp1out) vddio2 p2[4] (gpio) p2[3] (gpio) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpio) p15[4] (gpio) p6[3] (gpio) p6[2] (gpio) p6[1] (gpio) p6[0] (gpio) vddd vssd vccd p4[7] (gpio) p4[6] (gpio) p4[5] (gpio) p4[4] (gpio) p4[3] (gpio) p4[2] (gpio) p0[7] (gpio, idac2) p0[6] (gpio, idac0) p0[5] (gpio, opamp2-) p0[4] (gpio, opamp2+) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 lines show vddio to i/o supply association [11] [11] [12] [12] [12] [12] [12] [12] notes 11. pins are do not use (dnu) on devices with out usb. the pin must be left floating. 12. this feature on select devices only. see ordering information on page 116 for details. 13. the center pad on the qfn package should be connected to digital ground (vssd) for best mechanical, thermal, and electrical performance. if not connected to ground, it should be electrically floate d and not connected to any other signal.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 9 of 131 figure 2-7. example schematic for 100-pin tqfp part with power connections note the two vccd pins must be connected together with as short a trace as possible. a trace under the device is recommended, as shown in figure 2-8 on page 10. vssb 10 ind 11 vboost 12 vbat 13 vssd 14 xres 15 vddd 37 vssd 38 vccd 39 vcca 63 vssa 64 vdda 65 vssd 66 vccd 86 vssd 87 vddd 88 sio, p12[2] 67 sio, p12[3] 68 p4[0] 69 p4[1] 70 oa2out, p0[0] 71 oa0out, p0[1] 72 oa0+, p0[2] 73 oa0-, ref0, p0[3] 74 vddio0 75 oa2+, p0[4] 76 oa2-, p0[5] 77 idac0, p0[6] 78 idac2, p0[7] 79 p4[2] 80 p4[3] 81 p4[4] 82 p4[5] 83 p4[6] 84 p4[7] 85 p5[0] 16 p5[1] 17 p5[2] 18 p5[3] 19 p1[0], swdio, tms 20 p1[1], swdck, tck 21 p1[2] 22 p1[3], swv, tdo 23 p1[4], tdi 24 p1[5], ntrst 25 vddio1 26 p1[6] 27 p1[7] 28 p12[6], sio 29 p12[7], sio 30 p5[4] 31 p5[5] 32 p5[6] 33 p5[7] 34 usb d+, p15[6] 35 usb d-, p15[7] 36 p6[7] 9 p6[0] 89 p6[1] 90 p6[2] 91 p6[3] 92 p15[4] 93 p15[5] 94 p2[0] 95 p2[1] 96 p2[2] 97 p2[3] 98 p2[4] 99 vddio2 100 p2[5] 1 p2[6] 2 p2[7] 3 p12[4], sio 4 p12[5], sio 5 p6[4] 6 p6[5] 7 p6[6] 8 nc 40 nc 41 p15[0], mhzxout 42 p15[1], mhzxin 43 p3[0], idac1 44 p3[1], idac3 45 p3[2], oa3-, ref1 46 p3[3], oa3+ 47 p3[4], oa1- 48 p3[5], oa1+ 49 vddio3 50 oa1out, p3[6] 51 oa3out, p3[7] 52 sio, p12[0] 53 sio, p12[1] 54 khzxout, p15[2] 55 khzxin, p15[3] 56 nc 57 nc 58 nc 59 nc 60 nc 61 nc 62 vssd vdda vcca vccd vssd vddd vssd vddd vddd vssd vssa vssa vssd vssd vssd vssd 0.1 uf c8 vssd vddd vddd vddd vddd vddd vssd 1 uf c9 0.1 uf c10 0.1 uf c11 0.1 uf c16 0.1 uf c12 0.1 uf c6 0.1 uf c2 1 uf c15 1 uf c1 vssd vddd vssd vdda vssd vccd 1 uf c17 vssa vdda
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 10 of 131 figure 2-8. example pcb layout for 100-pin tqfp part for optimal analog performance 3. pin descriptions idac0, idac1, idac2, idac3. low resistance output pin for high current dacs (idac). opamp0out, opamp1out [15] , opamp2out, opamp3out [15] . high current output of uncommitted opamp. [14] extref0, extref1. external reference input to the analog system. opamp0?, opamp1? [15] , opamp2?, opamp3? [15] . inverting input to uncommitted opamp. opamp0+, opamp1+ [15] , opamp2+, opamp3+ [15] . noninverting input to uncommitted opamp. gpio. general purpose i/o pin provid es interfaces to the cpu, digital peripherals, analog peripherals, interrupts, lcd segment drive, and capsense. [14] i2c0: scl, i2c1: scl. i 2 c scl line providing wake from sleep on an address match. any i/o pin can be used for i 2 c scl if wake from sleep is not required. i2c0: sda, i2c1: sda. i 2 c sda line providing wake from sleep on an address match. any i/o pin can be used for i 2 c sda if wake from sleep is not required. ind. inductor connection to boost pump. khz xtal: xo, khz xtal: xi. 32.768 khz crystal oscillator pin. mhz xtal: xo, mhz xtal: xi. 4 to 25 mhz crystal oscillator pin. ntrst. optional jtag test reset programming and debug port connection to reset the jtag connection. sio. special i/o provides interfaces to the cpu, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. swdck. serial wire debug clock programming and debug port connection. swdio. serial wire debug input and output programming and debug port connection. swv. single wire viewer debug output. tck. jtag test clock programming and debug port connection. tdi. jtag test data in programming and debug port connection. tdo. jtag test data out programming and debug port connection. tms. jtag test mode select programming and debug port connection. usbio, d+. provides d+ connection directly to a usb 2.0 bus. may be used as a digital i/o pin. pins are do not use (dnu) on devices without usb. usbio, d?. provides d? connection directly to a usb 2.0 bus. may be used as a digital i/o pin. pins are do not use (dnu) on devices without usb. vboost. power sense connection to boost pump. vbat. battery supply to boost pump. vddd vssd vdda vssa vssd plane vssa plane notes 14. gpios with opamp outputs are not recommended for use with capsense. 15. this feature on select devices only. see ordering information on page 116 for details.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 11 of 131 vcca. output of the analog co re regulator or the input to the analog core. requires a 1uf capacitor to vssa. the regulator output is not designed to drive external circuits. note that if you use the device with an external core regulator (externally regulated mode), th e voltage applied to this pin must not exceed the allowable range of 1.71 v to 1.89 v. when using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. for details see power system on page 29. vccd. output of the digital core regulator or the input to the digital core. the two vccd pins must be shorted together, with the trace between them as short as possible, and a 1uf capacitor to vssd. the regulator output is not designed to drive external circuits. note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 v to 1.89 v. when using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. for details see power system on page 29. vdda. supply for all analog peripherals and analog core regulator. vdda must be the highest voltage present on the device. all other supply pins must be less than or equal to vdda. vddd. supply for all digital peripherals and digital core regulator. vddd must be less than or equal to vdda. vssa. ground for all analog peripherals. vssb. ground connection for boost pump. vssd. ground for all digital logic and i/o pins. vddio0, vddio1, vddio2, vddio3. supply for i/o pins. see pinouts for specific i/o pin to vddio mapping. each vddio must be tied to a valid operating voltage (1.71 v to 5.5 v), and must be less than or equal to vdda. xres (and configurable xres ). external reset pin. active low with internal pull-up. pin p1[2] may be configured to be a xres pin; see ?nonvolatile latches (nvls)? on page 22. 4. cpu 4.1 8051 cpu the cy8c36 devices use a single cycle 8051 cpu, which is fully compatible with the original mcs-51 instruction set. the cy8c36 family uses a pipelined risc architecture, which executes most instructions in 1 to 2 cycles to provide peak performance of up to 33 mips wi th an average of 2 cycles per instruction. the singl e cycle 8051 cpu runs ten times faster than a standard 8051 processor. the 8051 cpu subsystem includes these features: ? single cycle 8051 cpu ? up to 64 kb of flash memory, up to 2 kb of eeprom, and up to 8 kb of sram ? 512-byte instruction cache between cpu and flash ? programmable nested vector interrupt controller ? dma controller ? peripheral hub (phub) ? external memory interface (emif)
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 12 of 131 4.2 addressing modes the following addressing modes are supported by the 8051: ? direct addressing: the operand is specified by a direct 8-bit address field. only the internal ram and the sfrs can be accessed using this mode. ? indirect addressing: the instruct ion specifies the register which contains the address of the oper and. the registers r0 or r1 are used to specify the 8-bit address, while the data pointer (dptr) register is used to specify the 16-bit address. ? register addressing: certain instructions access one of the registers (r0 to r7) in the sp ecified register bank. these instructions are more efficient because there is no need for an address field. ? register specific instructions: so me instructions are specific to certain registers. for example, some instructions always act on the accumulator. in this case, there is no need to specify the operand. ? immediate constants: some instru ctions carry the value of the constants directly instead of an address. ? indexed addressing: this type of addressing can be used only for a read of the program memory. this mode uses the data pointer as the base and the accumulator value as an offset to read a program memory. ? bit addressing: in this mode, the operand is one of 256 bits. 4.3 instruction set the 8051 instruction set is highly optimized for 8-bit handling and boolean operations. the types of instructions supported include: ? arithmetic instructions ? logical instructions ? data transfer instructions ? boolean instructions ? program branching instructions 4.3.1 instruction set summary 4.3.1.1 arithmetic instructions arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. table 4-1 on page 13 lists the differ ent arithmetic instructions.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 13 of 131 4.3.1.2 logical instructions the logical instructions perform boolean operations such as and, or, xor on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. the boolean operations on the bytes are performed on the bit-by-bit basis. table 4-2 on page 13 shows the list of logical instructions and their description. table 4-1. arithmetic instructions mnemonic description bytes cycles add a,rn add register to accumulator 1 1 add a,direct add direct byte to accumulator 2 2 add a,@ri add indirect ram to accumulator 1 2 add a,#data add immediate data to accumulator 2 2 addc a,rn add register to accumulator with carry 1 1 addc a,direct add direct byte to accumulator with carry 2 2 addc a,@ri add indirect ram to accumulator with carry 1 2 addc a,#data add immediate data to accumulator with carry 2 2 subb a,rn subtract register fr om accumulator with borrow 1 1 subb a,direct subtract direct byte from accumulator with borrow 2 2 subb a,@ri subtract indirect ram from accumulator with borrow 1 2 subb a,#data subtract immediate data from accumulator with borrow 2 2 inc a increment accumulator 1 1 inc rn increment register 1 2 inc direct increment direct byte 2 3 inc @ri increment indirect ram 1 3 dec a decrement accumulator 1 1 dec rn decrement register 1 2 dec direct decrement direct byte 2 3 dec @ri decrement indirect ram 1 3 inc dptr increment data pointer 1 1 mul multiply accumulator and b 1 2 div divide accumulator by b 1 6 daa decimal adjust accumulator 1 3 table 4-2. logical instructions mnemonic description bytes cycles anl a,rn and register to accumulator 1 1 anl a,direct and direct byte to accumulator 2 2 anl a,@ri and indirect ram to accumulator 1 2 anl a,#data and immediate data to accumulator 2 2 anl direct, a and accumulator to direct byte 2 3 anl direct, #data and immediate data to direct byte 3 3 orl a,rn or register to accumulator 1 1 orl a,direct or direct by te to accumulator 2 2 orl a,@ri or indirect ram to accumulator 1 2
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 14 of 131 4.3.1.3 data transfer instructions the data transfer instructions are of three types: the core ram, xdata ram, and the lookup tables. the core ram transfer includes transfer between any two core ram locations or sfrs. these instructions can use direct, indirect, register, and immediate addressing. the xdata ram transfer includes only the transfer between the accumulato r and the xdata ram location. it can use only indirect addressing. the lookup tables involve nothing but the read of program memory using the indexed addressing mode. ta b l e 4 - 3 lists the various data transfer instructions available. 4.3.1.4 boolean instructions the 8051 core has a separate bit-addressable memory location. it has 128 bits of bit addressable ram and a set of sfrs that are bit addressable. the instruction set includes the whole menu of bit operations such as move, set, clear, toggle, or, and and instructions and the condit ional jump instructions. table 4-4 on page 15 lists the available boolean instructions. orl a,#data or immediate data to accumulator 2 2 orl direct, a or accumulator to direct byte 2 3 orl direct, #data or immediate data to direct byte 3 3 xrl a,rn xor register to accumulator 1 1 xrl a,direct xor direct byte to accumulator 2 2 xrl a,@ri xor indirect ram to accumulator 1 2 xrl a,#data xor immediate data to accumulator 2 2 xrl direct, a xor accumulator to direct byte 2 3 xrl direct, #data xor immediate data to direct byte 3 3 clr a clear accumulator 1 1 cpl a complement accumulator 1 1 rl a rotate accumulator left 1 1 rlc a rotate accumulato r left through carry 1 1 rr a rotate accumulator right 1 1 rrc a rotate accumulator right though carry 1 1 swap a swap nibbles within accumulator 1 1 table 4-2. logical instructions (continued) mnemonic description bytes cycles table 4-3. data transfer instructions mnemonic description bytes cycles mov a,rn move register to accumulator 1 1 mov a,direct move direct byte to accumulator 2 2 mov a,@ri move indirect ram to accumulator 1 2 mov a,#data move immediate data to accumulator 2 2 mov rn,a move accumulator to register 1 1 mov rn,direct move direct byte to register 2 3 mov rn, #data move immediate data to register 2 2 mov direct, a move accumulator to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 3 mov direct, #data move immediate data to direct byte 3 3 mov @ri, a move accumulator to indirect ram 1 2
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 15 of 131 mov @ri, direct move direct byte to indirect ram 2 3 mov @ri, #data move immediate data to indirect ram 2 2 mov dptr, #data16 load data pointer with 16 bit constant 3 3 movc a, @a+dptr move code byte rela tive to dptr to accumulator 1 5 movc a, @a + pc move code byte re lative to pc to accumulator 1 4 movx a,@ri move external ram (8-bit) to accumulator 1 4 movx a, @dptr move external ram (16-bit) to accumulator 1 3 movx @ri, a move accumulator to external ram (8-bit) 1 5 movx @dptr, a move accumulator to external ram (16-bit) 1 4 push direct push direct byte onto stack 2 3 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with accumulator 1 2 xch a, direct exchange direct byte with accumulator 2 3 xch a, @ri exchange indirect ram with accumulator 1 3 xchd a, @ri exchange low order indirect digit ram with accumulator 1 3 table 4-4. boolean instructions mnemonic description bytes cycles clr c clear carry 1 1 clr bit clear direct bit 2 3 setb c set carry 1 1 setb bit set direct bit 2 3 cpl c complement carry 1 1 cpl bit complement direct bit 2 3 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 3 jc rel jump if carry is set 2 3 jnc rel jump if no carry is set 2 3 jb bit, rel jump if direct bit is set 3 5 jnb bit, rel jump if direct bit is not set 3 5 jbc bit, rel jump if direct bit is set and clear bit 3 5 table 4-3. data transfer instructions (continued) mnemonic description bytes cycles
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 16 of 131 4.3.1.5 program branching instructions the 8051 supports a set of conditional and unconditional jump in structions that help to modify the program execution flow. table 4-5 shows the list of jump instructions. 4.4 dma and phub the phub and the dma controller are responsible for data transfer between the cpu and peripherals, and also data transfers between peripherals. the phub and dma also control device configuration during boot. the phub consists of: ? a central hub that includes th e dma controller, arbiter, and router ? multiple spokes that radiate outward from the hub to most peripherals there are two phub masters: the cpu and the dma controller. both masters may initiate transactions on the bus. the dma channels can handle peripheral communication without cpu intervention. the arbiter in t he central hub determines which dma channel is the highest priority if there are multiple requests. 4.4.1 phub features ? cpu and dma controller are both bus masters to the phub ? eight multi-layer ahb bus parall el access paths (spokes) for peripheral access ? simultaneous cpu and dma access to peripherals located on different spokes ? simultaneous dma source and de stination burst transactions on different spokes ? supports 8-, 16-, 24-, and 32-bit addressing and data table 4-5. jump instructions mnemonic description bytes cycles acall addr11 absolute subroutine call 2 4 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 4 reti return from interrupt 1 4 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a + dptr jump indirect relative to dptr 1 5 jz rel jump if accumulator is zero 2 4 jnz rel jump if accumulator is nonzero 2 4 cjne a,direct, rel compare direct byte to accumulator and jump if not equal 3 5 cjne a, #data, rel compare immediate data to accumulator and jump if not equal 3 4 cjne rn, #data, rel compare immediate data to register and jump if not equal 3 4 cjne @ri, #data, rel compare immediate data to indirect ram and jump if not equal 3 5 djnz rn,rel decrement register and jump if not zero 2 4 djnz direct, rel decrement direct byte and jump if not zero 3 5 nop no operation 1 1 table 4-6. phub spokes and peripherals phub spokes peripherals 0 sram 1 ios , picu , emif 2 phub local configuration, power manager , clocks , ic , swv , eeprom , flash programming interface 3 analog interface and trim , decimator 4 usb , can , i 2 c , timers, counters, and pwms 5 dfb 6 udbs group 1 7 udbs group 2
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 17 of 131 4.4.2 dma features ? 24 dma channels ? each channel has one or more transaction descriptors (td) to configure channel behavior. up to 128 total tds can be defined ? tds can be dynamically updated ? eight levels of priority per channel ? any digitally routable signal, the cpu, or another dma channel, can trigger a transaction ? each channel can generate up to two interrupts per transfer ? transactions can be stalled or canceled ? supports transaction size of infinite or 1 to 64 kb ? tds may be nested and/or chained for complex transactions 4.4.3 priority levels the cpu always has higher priority than the dma controller when their accesses require the same bus resources. due to the system architecture, the cpu c an never starve the dma. dma channels of higher priority (lower priority number) may interrupt current dma transfers. in the case of an interrupt, the current transfer is allowed to complete its current transaction. to ensure latency limits when multiple dma accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. if a tie occurs on two dma requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. the round robin allocation can be disabled for each dma channel, allowing it to always be at the head of the line. priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in ta b l e 4 - 7 after the cpu and dma priority levels 0 and 1 have satisfied their requirements. when the fairness algorithm is disabled, dma access is granted based solely on the priority level; no bus bandwidth guarantees are made. 4.4.4 transaction modes supported the flexible configuration of each dma channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. general use cases include, but are not limited to: 4.4.4.1 simple dma in a simple dma case, a single td transfers data between a source and sink (peripherals or memory location). the basic timing diagrams of dma read and write cycles shown in figure 4-1 . for more description on ot her transfer modes, refer to the technical reference manual. figure 4-1. dma timing diagram 4.4.4.2 auto repeat dma auto repeat dma is typically used when a static pattern is repetitively read from system memo ry and written to a peripheral. this is done with a single td that chains to itself. 4.4.4.3 ping pong dma a ping pong dma case uses double buffering to allow one buffer to be filled by one client while an other client is consuming the data previously received in the other buffer. in its simplest form, this is done by chaining two tds together so that each td calls the opposite td when complete. 4.4.4.4 circular dma circular dma is similar to ping pong dma except it contains more than two buffers. in this case there are multiple tds; after the last td is complete it chains back to the first td. table 4-7. priority levels priority level % bus bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4 12.5 56.2 63.1 71.5 clk addr 16/32 write data ready basic dma read transfer without wait states ab data (a) address phase data phase ab address phase data phase clk write data ready data (a) basic dma write transfer without wait states addr 16/32
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 18 of 131 4.4.4.5 scatter gather dma in the case of scatter gather dma, there are multiple noncontiguous sources or destin ations that are required to effectively carry out an overall dma transaction. for example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. scatter gather dma allows the segments to be concatenated together by using multiple tds in a chain. the chain gathers the data from the multiple locations. a similar concept applies for the reception of data onto the device. certain parts of the received data may need to be scattered to various locati ons in memory for software processing convenience. each td in the chain specifies the location for each discrete element in the chain. 4.4.4.6 packet queuing dma packet queuing dma is similar to scatter gather dma but specifically refers to packet protocols. with these protocols, there may be separate configurat ion, data, and status phases associated with sending or receiving a packet. for instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. the cpu can set up this configuration information anywhere in system memory and copy it with a simple td to the peripheral. after the configuration phase, a data phase td (or a series of data phase tds) can begin (potentially using scatter gather). when the data phase td(s) finish, a status phase td can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory s pecified by the cpu for later inspection. multiple sets of configuration, data, and status phase ?subchains? can be strung together to create larger chains that transmit multiple packets in this way. a similar concept exists in the opposite di rection to receive the packets. 4.4.4.7 nested dma one td may modify another td, as the td configuration space is memory mapped similar to any other peripheral. for example, a first td loads a second td?s configuration and then calls the second td. the second td moves data as required by the application. when complete, th e second td calls the first td, which again updates the second td?s configuration. this process repeats as often as necessary. 4.5 interrupt controller the interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. the interrupt controller provides enhanced features not found on original 8051 interrupt controllers: ? thirty-two interrupt vectors ? jumps directly to isr anywhere in code space with dynamic vector addresses ? multiple sources for each vector ? flexible interrupt to vector matching ? each interrupt vector is independently enabled or disabled ? each interrupt can be dynamically assigned one of eight priorities ? eight level nestable interrupts ? multiple i/o interrupt vectors ? software can send interrupts ? software can clear pending interrupts when an interrupt is pending, the current instruction is completed and the program coun ter is pushed onto the stack. code execution then jumps to the program address provided by the vector. after the isr is comp leted, a reti instruction is executed and returns execution to the instruction following the previously interrupted instruction. to do this the reti instruction pops the program counter from the stack. if the same priority level is assi gned to two or more interrupts, the interrupt with the lower vector number is executed first. each interrupt vector may choose from three interrupt sources: fixed function, dma, and udb. the fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. the dma interrupt sources provide direct connections to the two dma interrupt sources provided per dma channel. the third interrupt source for vectors is from the udb digital routing array. this allows any digital signal available to the udb array to be used as an interrupt source. fixed function interrupts and all interrupt sources may be routed to any interrupt vector usin g the udb interrupt source connections. figure 4-2 on page 19 represents typical flow of events when an interrupt triggered. figure 4-3 on page 20 shows the interrupt structure and priority polling.
document number: 001-53413 rev. *o page 19 of 131 psoc ? 3: cy8c36 family data sheet figure 4-2. interrupt processing timing diagram notes 1: interrupt triggered asynchronous to the clock 2: the pend bit is set on next active clock edge to indicate the interrupt arrival 3: post bit is set following the pend bit 4: interrupt request and t he interrupt number sent to cpu core af ter evaluation priority (takes 3 clocks) 5: isr address is posted to cpu core for branching 6: cpu acknowledges the interrupt request 7: isr address is read by cpu for branching 8, 9: pend and post bits are cleared res pectively after receiving the ira from core 10: ira bit is cleared after completing the current instruction an d starting the instruction exec ution from isr location (takes 7 cycles) 11: irc is set to indicate the completion of isr, ac tive int. status is rest ored with previous status the total interrupt latency (isr execution) = post + pend + irq + ira + completing current instruction and branching = 1+1+1+2+7 cycles = 12 cycles the active interrupt isr address is posted to core interrupt generation and posting to cpu the active interrupt number is posted to core interrupt request sent to core for processing interrupt is posted to ascertain the priority pend bit is set on next clock active edge arrival of new interrupt clk int_input pend post irq active_int_num (#10) int_vect_addr ira irc s s s s s s s s s s s 0x0010 na cpu response int. state clear completing current instruction and branching to vector address complete isr and return na irq cleared after receiving ira post and pend bits cleared after irq is sleared 0x0000 na time 1 2 3 4 5 6 7 8 9 10 11
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 20 of 131 figure 4-3. interrupt structure interrupts 0 to 31 from udbs interrupt routing logic to select 32 sources interrupt 2 to 30 0 1 31 individual enable disable bits global enable disable bit interrupt enable/ disable, pend and post logic interrupts form fixed function blocks, dma and udbs 8 level priority decoder for all interrupts polling sequence highest priority lowest priority interrupt polling logic irc ira irq 0 to 31 [15:0] active_int_num int_vect_addr interrupts 0 to 31 from fixed function blocks interrupts 0 to 31 from dma table 4-8. interrupt vector table # fixed function dma udb 0 lvd phub_termout0[0] udb_intr[0] 1 cache/ecc phub_termout0[1] udb_intr[1] 2 reserved phub_termout0[2] udb_intr[2] 3 sleep (pwr mgr) phub_te rmout0[3] udb_intr[3] 4 picu[0] phub_termout 0[4] udb_intr[4] 5 picu[1] phub_termout 0[5] udb_intr[5] 6 picu[2] phub_termout 0[6] udb_intr[6] 7 picu[3] phub_termout 0[7] udb_intr[7] 8 picu[4] phub_termout 0[8] udb_intr[8] 9 picu[5] phub_termout 0[9] udb_intr[9] 10 picu[6] phub_termout 0[10] udb_intr[10] 11 picu[12] phub_termout 0[11] udb_intr[11] 12 picu[15] phub_termout 0[12] udb_intr[12] 13 comparators combined phub _termout0[13] udb_intr[13] 14 switched caps combined phub_termout0[14] udb_intr[14] 15 i 2 c phub_termout0[15] udb_intr[15] 16 can phub_termout1[0] udb_intr[16] 17 timer/counter0 phub_te rmout1[1] udb_intr[17] 18 timer/counter1 phub_te rmout1[2] udb_intr[18] 19 timer/counter2 phub_te rmout1[3] udb_intr[19] 20 timer/counter3 phub_te rmout1[4] udb_intr[20]
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 21 of 131 5. memory 5.1 static ram cy8c36 static ram (sram) is used for temporary data storage. up to 8 kb of sram is provided and can be accessed by the 8051 or the dma controller. see memory map on page 23. simultaneous access of sram by the 8051 and the dma controller is possible if diff erent 4-kb blocks are accessed. 5.2 flash program memory flash memory in psoc devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ecc data. the main flash memory area contains up to 64 kb of user program space. up to an additional 8 kb of flash space is available for ecc. if ecc is not used this space can store device configuration data and bulk user data. user code may not be run out of the ecc flash memory section. ecc can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. the cpu reads instructions located in flash through a cache controller. this improves instru ction execution rate and reduces system power consumption by requiring less frequent flash access. the cache has 8 lines at 64 bytes per line for a total of 512 bytes. it is fully associative, automatically controls flash power, and can be enabled or disabled. if ecc is enabled, the cache controller also performs error checking and correction, and interrupt generation. flash programming is performed through a special interface and preempts code execution out of flash. the flash programming interface performs flash erasing, programming and setting code protection levels. flash in-syst em serial programming (issp), typically used for production programming, is possible through both the swd and jtag interf aces. in-system programming, typically used for bootloaders, is also possible using serial interfaces such as i 2 c, usb, uart, and spi, or any communications protocol. 5.3 flash security all psoc devices include a flexible flash-protection model that prevents access and visibility to on-chip flash memory. this prevents duplication or reverse en gineering of proprietary code. flash memory is organized in blo cks, where each block contains 256 bytes of program or data and 32 bytes of ecc or configuration data. a total of up to 256 blocks is provided on 64-kb flash devices. the device offers the ability to assign one of four protection levels to each row of flash. table 5-1 lists the protection modes available. flash protection levels can only be changed by performing a complete flash erase. the full protection and field upgrade settings disable external access (through a debugging tool such as psoc creator, for example). if your application requires code update through a boot loader, then use the field upgrade setting. use the unpr otected setting only when no security is needed in your application. the psoc device also offers an advanced security feat ure called device security that permanently disables all test, programming, and debug ports, protecting your application fr om external access (see device security on page 65). for information about how to take full advantage of the security features in psoc, see the psoc 3 trm . disclaimer note the following details of the fl ash code protection features on cypress devices. cypress products meet the specifications contained in their particular cypress data sheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. an y of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? 21 usb sof int phub_termout1[5] udb_intr[21] 22 usb arb int phub_termout1[6] udb_intr[22] 23 usb bus int phub_termout1[7] udb_intr[23] 24 usb endpoint[0] phub_termout1[8] udb_intr[24] 25 usb endpoint data phub_termout1[9] udb_intr[25] 26 reserved phub_termout1[10] udb_intr[26] 27 lcd phub_termout1[11] udb_intr[27] 28 dfb int phub_termout1[12] udb_intr[28] 29 decimator int phub_termout1[13] udb_intr[29] 30 phub error int phub_termout1[14] udb_intr[30] 31 eeprom fault int phub_t ermout1[15] udb_intr[31] table 4-8. interrupt vector table (continued) # fixed function dma udb table 5-1. flash protection protection setting allowed not allowed unprotected external read and write + internal read and write ? factory upgrade external write + internal read and write external read field upgrade internal read and write external read and write full protection internal read external read and write + internal write
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 22 of 131 cypress is willing to work with the customer who is concerned about the integrity of their code . code protection is constantly evolving. we at cypress are committed to continuously improving the code protecti on features of our products. 5.4 eeprom psoc eeprom memory is a byte-addressable non volatile memory. the cy8c36 has up to 2 kb of eeprom memory to store user data. reads from eeprom are random access at the byte level. reads are done directly; writes are done by sending write commands to an eeprom programming interface. cpu code execution can continue from flash during eeprom writes. eeprom is erasable and writeable at the row level. the eeprom is divided into 128 rows of 16 bytes each. the cpu can not execute out of eeprom. ther e is no ecc hardware associated with eeprom. if ecc is required it must be handled in firmware. 5.5 nonvolatile latches (nvls) psoc has a 4-byte array of nonvolatile latches (nvls) that are used to configure the device at reset. the nvl register map is s hown in ta b l e 5 - 2 . the details for individual fields and their factory default settings are shown in table 5-3 :. although psoc creator provides support for modifying the device configuration nvls, the number of nvl erase / write cycles is l imited ? see ?nonvolatile latches (nvl))? on page 104 . table 5-2. device configuration nvl register map register address 7 6 5 4 3 2 1 0 0x00 prt3rdm[1:0] prt2rdm[1:0] prt1rdm[1:0] prt0rdm[1:0] 0x01 prt12rdm[1:0] prt6rdm[1:0] prt5rdm[1:0] prt4rdm[1:0] 0x02 xresmen prt15rdm[1:0] 0x03 dig_phs_dly[3:0] eccen dps[1:0] cfgspeed table 5-3. fields and factory default settings field description settings prtxrdm[1:0] controls reset drive mode of the corresponding io port. see ?reset configuration? on page 40. all pins of the port are set to the same mode. 00b (default) - high impedance analog 01b - high impedance digital 10b - resistive pull up 11b - resistive pull down xresmen controls whether pin p1[2 ] is used as a gpio or as an external reset. see ?pin descriptions? on page 10, xres description. 0 (default for 68-pin and 100-pin parts) - gpio 1 (default for 48-pin parts) - external reset cfgspeed controls the speed of the imo-based clock during the device boot process, for fa ster boot or low-power operation 0 (default) - 12 mhz imo 1 - 48 mhz imo dps{1:0] controls the usage of various p1 pins as a debug port. see ?programming, debug interfaces, resources? on page 62. 00b - 5-wire jtag 01b (default) - 4-wire jtag 10b - swd 11b - debug ports disabled eccen controls whether ecc flash is used for ecc or for general configuration and data storage. see ?flash program memory? on page 21. 0 (default) - ecc disabled 1 - ecc enabled dig_phs_dly[3:0] selects the digital clock phase delay. see the trm for details.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 23 of 131 5.6 external memory interface cy8c36 provides an external memory interface (emif) for connecting to external memory devices. the connection allows read and write accesses to external memories. the emif operates in conjunction with udbs, i/o ports, and other hardware to generate external memory address and control signals. at 33 mhz, each memo ry access cycle takes four bus clock cycles. figure 5-1 is the emif block diagram. the emif supports synchronous and asynchronous memories. the cy8c36 supports only one type of external memory device at a time. external memory can be accessed through the 8051 xdata space; up to 24 address bits can be used. see xdata space on page 25. the memory can be 8 or 16 bits wide. figure 5-1. emif block diagram 5.7 memory map the cy8c36 8051 memory map is very similar to the mcs-51 memory map. 5.7.1 code space the cy8c36 8051 code space is 64 kb. only main flash exists in this space. see the ?flash program memory? section on page 21. 5.7.2 internal data space the cy8c36 8051 internal data space is 384 bytes, compressed within a 256-byte space. this space consists of 256 bytes of ram (in addition to the sram mentioned in ?static ram? on page 21) and a 128-byte space for special function registers (sfrs). see figure 5-2 . the lowest 32 bytes are used for four banks of registers r0-r7. the nex t 16 bytes are bit-addressable. phub io if udb emif io ports io ports io ports data, address, and control signals data, address, and control signals address signals data signals control signals data, address, and control signals em control signals other control signals dsi dynamic output control dsi to port control external_ mem_ data[15:0] external_ mem_ addr[23:0]
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 24 of 131 figure 5-2. 8051 internal data space in addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct or indirect addressing. with direct addressing mode, the upper 128 bytes map to the sfrs. with indirect addressing mode, the upper 128 bytes map to ram. stack operations use indirect addressing; the 8051 stack space is 256 bytes. see the ?addressing modes? section on page 12. 5.7.3 sfrs the special function register (sfr) space provides access to fr equently accessed registers. the memory map for the sfr memory space is shown in table 5-4 . the cy8c36 family provides the standard set of registers found on industry standard 8051 devices. in addition, the cy8c36 devices add sfrs to provide direct access to the i/o ports on the device. the following sections describe the sfrs added to the cy8c36 family. 5.7.4 xdata space access sfrs the 8051 core features dual dp tr registers for faster data transfer operations. the data pointer select sfr, dps, selects which data pointer register, dptr 0 or dptr1, is used for the following instructions: ? movx @dptr, a ? movx a, @dptr ? movc a, @a+dptr ? jmp @a+dptr ? inc dptr ? mov dptr, #data16 the extended data pointer sfrs, dpx0, dpx1, mxax, and p2ax, hold the most significant parts of memory addresses during access to the xdata space. these sfrs are used only with the movx instructions. during a movx instruction using the dptr0/dptr1 register, the most significant byte of the address is always equal to the contents of dpx0/dpx1. during a movx instruction using t he r0 or r1 register, the most significant byte of the address is always equal to the contents of mxax, and the next most significant byte is always equal to the contents of p2ax. upper core ram shared with stack space (indirect addressing) sfr special function registers (direct addressing) lower core ram shared with stack space (direct and indirect addressing) bit-addressable area 4 banks, r0-r7 each 0xff 0x80 0x7f 0x30 0x2f 0x20 0x1f 0x00 table 5-4. sfr map address 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 0f8sfrprt15drsfrprt15pssfrprt15sel????? 0f0b ? sfrprt12sel????? 0e8sfrprt12drsfrprt12psmxax ????? 0e0acc ? ? ????? 0d8sfrprt6drsfrprt6pssfrprt6sel????? 0d0psw ? ? ????? 0c8sfrprt5drsfrprt5pssfrprt5sel????? 0c0sfrprt4drsfrprt4pssfrprt4sel????? 0b8? ? ? ????? 0b0sfrprt3drsfrprt3pssfrprt3sel????? 0a8ie ? ? ????? 0a0p2ax ? sfrprt1sel????? 098sfrprt2drsfrprt2pssfrprt2sel????? 090 sfrprt1dr sfrprt1ps ? dpx0 ? dpx1 ? ? 088? sfrprt0pssfrprt0sel????? 080 sfrprt0dr sp dpl0 dph0 dpl1 dph1 dps ?
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 25 of 131 5.7.5 i/o port sfrs the i/o ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, lcd, and access to peripherals through the dsi. full information on i/o ports is found in i/o system and routing on page 34. i/o ports are linked to the cpu through the phub and are also available in the sfrs. using the sfrs allows faster access to a limited set of i/o port registers, while using the phub allows boot configuration and access to all i/o port registers. each sfr supported i/o port provides three sfrs: ? sfrprtxdr sets the output data state of the port (where is port number and includes ports 0?6, 12 and 15). ? the sfrprtxsel selects whether the phub prtxdr register or the sfrprtxdr cont rols each pin?s output buffer within the port. if a sfrprtxsel[y] bit is high, the corresponding sfrprtxdr[y] bit se ts the output state for that pin. if a sfrprtxsel[y] bit is low, the corresponding prtxdr[y] bit sets the output state of the pin (where y varies from 0 to 7). ? the sfrprtxps is a read only regi ster that contains pin state values of the port pins. 5.7.5.1 xdata space the 8051 xdata space is 24-bit, or 16 mb in size. the majority of this space is not ?external??it is used by on-chip components. see ta b l e 5 - 5 . external, that is, off-chip, memory can be accessed using the emif. see external memory interface on page 23. table 5-5. xdata data address map address range purpose 000 0000 ? 000 1fff sram 000 4000 ? 000 42ff clocking, plls, and oscillators 000 4300 ? 000 43ff power management 000 4400 ? 000 44ff interrupt controller 000 4500 ? 000 45ff ports interrupt control 000 4700 ? 000 47ff flash programming interface 000 4800 - 000 48ff cache controller 000 4900 ? 000 49ff i 2 c controller 000 4e00 ? 000 4eff decimator 000 4f00 ? 000 4fff fixed timer/counter/pwms 000 5000 ? 000 51ff i/o ports control 000 5400 ? 000 54ff external memory interface (emif) control registers 000 5800 ? 000 5fff analog subsystem interface 000 6000 ? 000 60ff usb controller 000 6400 ? 000 6fff udb configuration 000 7000 ? 000 7fff phub configuration 000 8000 ? 000 8fff eeprom 000 a000 ? 000 a400 can 000 c000 ? 000 c800 digital filter block 001 0000 ? 001 ffff digital interconnect configuration 005 0220 ? 005 02f0 debug controller 008 0000 ? 008 1fff flash ecc bytes 080 0000 ? 0ff ffff external memory interface
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 26 of 131 6. system integration 6.1 clocking system the clocking system generates, di vides, and distributes clocks throughout the psoc system. for the majority of systems, no external crystal is required. the imo and pll together can generate up to a 66 mhz clock, accurate to 1% over voltage and temperature. additional internal and external clock sources allow each design to optimize accuracy, power, and cost. any of the clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and udbs for anything the user wants, for example a uart baud rate generator. clock generation and distribution is automatically configured through the psoc creator ide graphical interface. this is based on the complete system?s requ irements. it greatly speeds the design process. psoc creator allows you to build clocking systems with minimal input. yo u can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. this is possible because of the programmability inherent in psoc. key features of the cl ocking system include: ? seven general purpose clock sources ? 3- to 62-mhz imo, 1% at 3 mhz ? 4- to 25-mhz external crystal oscillator (mhzeco) ? clock doubler provides a doubled clock frequency output for the usb block, see usb clock domain on page 29. ? dsi signal from an external i/o pin or other logic ? 24- to 67-mhz fractional p ll sourced from imo, mhzeco, or dsi ? 1-khz, 33-khz, 100-khz ilo for wdt and sleep timer ? 32.768-khz external crystal oscillator (khzeco) for rtc ? imo has a usb mode that auto locks to the usb bus clock requiring no external crystal for usb. (usb equipped parts only) ? independently sourced clock in all clock dividers ? eight 16-bit clock divider s for the digital system ? four 16-bit clock dividers for the analog system ? dedicated 16-bit divider for the bus clock ? dedicated 4-bit divider for the cpu clock ? automatic clock configuration in psoc creator
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 27 of 131 figure 6-1. clocking subsystem 6.1.1 internal oscillators 6.1.1.1 internal main oscillator in most designs the imo is the only clock source required, due to its 1% accuracy. the imo operates with no external components and outputs a stable clock. a factory trim for each frequency range is stored in the device. with the factory trim, tolerance varies from 1% at 3 mhz, up to 7% at 62 mhz. the imo, in conjunction with the p ll, allows generation of other clocks up to the device's maximum frequency (see phase-locked loop ). the imo provides clock outputs at 3, 6, 12, 24, 48, and 62 mhz. 6.1.1.2 clock doubler the clock doubler outputs a clock at twice the frequency of the input clock. the doubler worksa t input frequency of 24 mhz, providing 48 mhz for the usb. it can be configured to use a clock from the imo, mhzeco, or the dsi (external pin). 6.1.1.3 phase-locked loop the pll allows low frequency, high accuracy clocks to be multiplied to higher frequencies. this is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. table 6-1. oscillator summary source fmin tolerance at fmin fmax tolerance at fmax startup time imo 3 mhz 1% over voltage and temperature 62 mhz 7% 13 s max mhzeco 4 mhz crystal dependent 25 mhz crystal dependent 5 ms typ, max is crystal dependent dsi 0 mhz input dependent 66 mhz input dependent input dependent pll 24 mhz input dependent 67 mhz input dependent 250 s max doubler 48 mhz input dependent 48 mhz input dependent 1 s max ilo 1 khz ?50%, +100% 100 khz ?55%, +100% 15 ms max in lowest power mode khzeco 32 khz crystal dependent 32 khz crystal dependent 500 ms typ, max is crystal dependent 4-25 mhz eco 3-62 mhz imo 32 khz eco 1,33,100 khz ilo s k e w 7 7 digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit analog clock divider 16 bit bus clock divider 16 bit 48 mhz doubler for usb 24-67 mhz pll master mux external io or dsi 0-66 mhz s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit cpu clock divider 4 bit bus clock cpu clock
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 28 of 131 the pll block provides a mechanism for generating clock frequencies based upon a variety of input sources. the pll outputs clock frequencies in the range of 24 to 67 mhz. its input and feedback dividers supply 4032 discrete ratios to create almost any desired clock frequency. the accuracy of the pll output depends on the accuracy of the pll input source. the most common pll use is to mult iply the imo clock at 3 mhz, where it is most accurate, to generate the other clocks up to the device?s maximum frequency. the pll achieves phase lock within 250 s (verified by bit setting). it can be configured to use a clock from the imo, mhzeco or dsi (external pin). the pll clock source can be used until lock is complete and signaled with a lock bit. the lock signal can be routed through the dsi to generate an interrupt. disable the pll before entering low-power modes. 6.1.1.4 internal low-speed oscillator the ilo provides clock frequenci es for low-power consumption, including the watchdog timer, and sleep timer. the ilo generates up to three different clocks: 1 khz, 33 khz, and 100 khz. the 1-khz clock (clk1k) is typically used for a background ?heartbeat? timer. this clock inherently lends itself to low-power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (ctw). the central timewheel is a 1-khz, free-running, 13-bit counter clocked by the ilo. the central timewheel is always enabled, except in hibernate mode and when the cpu is stopped during debug on chip mode. it can be used to generate periodic interrupts for timing purposes or to wake the system from a low-power mode. firmware can reset the central timewheel. systems that require accurate timing should use the rtc capability instead of the central timewheel. the 100-khz clock (clk100k) can be used as a low power master clock. it can also generate time intervals using the fast timewheel. the fast timewheel is a 5-bit counter, clocked by the 100-khz clock. it features programmabl e settings and automatically resets when the terminal count is reached. an optional interrupt can be generated each time the terminal count is reached. this enables flexible, periodic interrupts of the cpu at a higher rate than is allowed using the central timewheel. the 33-khz clock (clk33k) comes from a divide-by-3 operation on clk100k. this output can be used as a reduced accuracy version of the 32.768-khz eco clock with no need for a crystal. 6.1.2 external oscillators 6.1.2.1 mhz external crystal oscillator the mhzeco provides high frequency, high precision clocking using an external crystal (see figure 6-2 ). it supports a wide variety of crystal types, in the range of 4 to 25 mhz. when used in conjunction with the pll, it c an generate other clocks up to the device's maximum frequency (see phase-locked loop ). the gpio pins connecting to the exte rnal crystal and capacitors are fixed. mhzeco accuracy depends on the crystal chosen. figure 6-2. mhzeco block diagram 6.1.2.2 32.768-khz eco the 32.768-khz external crystal o scillator (32khzeco) provides precision timing with minimal power consumption using an external 32.768-khz watch crystal (see figure 6-3 ). the 32khzeco also connects directly to the sleep timer and provides the source for the rtc. the rtc uses a 1-second interrupt to implement the rtc functionality in firmware. the oscillator works in two distinct power modes. this allows users to trade off power consumption with noise immunity from neighboring circuits. the gpio pins connected to the external crystal and capacitors are fixed. figure 6-3. 32khzeco block diagram it is recommended that the external 32.768-khz watch crystal have a load capacitance (cl) of 6 pf or 12.5 pf. check the crystal manufacturer's datasheet. the two external capacitors, cl1 and cl2, are typically of the same value, and their total capacitance, cl1cl2 / (cl1 + cl2), including pin and trace capacitance, should equal the crystal cl value. for more information, refer to application note an54439: psoc 3 and psoc 5 external oscillators . see also pin capacitance specifications in the ?gpio? section on page 75. xo (pin p15[0]) 4 ? 25 mhz crystal osc xclk_mhz 4 ? 25 mhz crystal capacitors external components xi (pin p15[1]) xo (pin p15[2]) 32 khz crystal osc xclk32k 32 khz crystal capacitors external components xi (pin p15[3])
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 29 of 131 6.1.2.3 digital system interconnect the dsi provides routing for clocks taken from external clock oscillators connected to i/o. the oscillators can also be generated within the device in the digital system and udbs. while the primary dsi clock input provides access to all clocking resources, up to eight other dsi clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. this is only possible if there are multiple precision clock sources. 6.1.3 clock distribution all seven clock sources are inputs to the central clock distribution system. the distribution system is designed to create multiple high precision clocks. these clocks are customized for the design?s requirements and eliminate the common problems found with limited resolution pre scalers attached to peripherals. the clock distribution system generates several types of clock trees. ? the master clock is used to select and supply the fastest clock in the system for general clock requirements and clock synchronization of the psoc device. ? bus clock 16-bit divider uses the master clock to generate the bus clock used for data transfers . bus clock is the source clock for the cpu clock divider. ? eight fully programmable 16-bit clock dividers generate digital system clocks for general us e in the digital system, as configured by the design?s requ irements. digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. examples include baud rate generators, accurate pwm periods, and timer clocks, and many others. if more than eight digital clock dividers are required, the universal digital bl ocks (udbs) and fixed function timer/counter/pwms can also genera te clocks. ? four 16-bit clock divi ders generate clocks for the analog system components that require clocking, such as adc and mixers. the analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. this is done to reduce analog system noise. each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and hi gher) that generates ~50% duty cycle clocks, master cl ock resynchronization logic, and deglitch logic. the outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an inpu t, allowing clock chaining of up to 32 bits. 6.1.4 usb clock domain the usb clock domain is unique in that it operates largely asynchronously from the main clock network. the usb logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process usb data. the usb logic requires a 48 mhz frequency. this frequency can be generated from different sources, including dsi clock at 48 mhz or doubled value of 24 mhz from internal oscillator, dsi signal, or crystal oscillator. 6.2 power system the power system consists of separate analog, digital, and i/o supply pins, labeled vdda, vddd, and vddio, respectively. it also includes two internal 1.8 v regulators that provide the digital (vccd) and analog (vcca) supplies for the internal core logic. the output pins of the regulators (vccd and vcca) and the vddio pins must have capacitors connected as shown in figure 6-4 . the two vccd pins must be shorted together, with as short a trace as possible, and connected to a 1-f 10% 5r capacitor. the power system also contains a sleep regulator, an i 2 c regulator, and a hibernate regulator.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 30 of 131 figure 6-4. psoc power system note the two vccd pins must be connected together with as short a trace as possible. a trace under the device is recommended, as shown in figure 2-8 on page 10. you can power the device in internally regulated mode, where the voltage applied to the v ddx pins is as high as 5.5 v, and the internal regulators provide the core voltages. in this mode, do not apply power to the v ccx pins, and do not tie the v ddx pins to the v ccx pins. you can also power the device in externally regul ated mode, that is, by directly powering the v ccd and v cca pins. in this configuration, the v ddd pins should be shorted to the v ccd pins and the v dda pin should be shorted to the v cca pin. the allowed supply range in this configuration is 1.71 v to 1.89 v. after power up in this c onfiguration, the internal regulato rs are on by default, and shou ld be disabled to reduce power consumption. vssb vddio2 vddio0 vddio3 vccd vddd vssd vccd vddd vssa vcca vdda digital regulators analog regulator analog domain digital domain i2c regulator sleep regulator hibernate regulator i/o supply i/o supply i/o supply i/o supply vddio2 vddio0 vddio3 vddio1 0.1 f 0.1 f 0.1 f 0.1 f vddd vddd 1 f 1 f vdda 0.1 f 0.1 f 0.1 f vddio1 vssd
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 31 of 131 6.2.1 power modes psoc 3 devices have four different power modes, as shown in ta b l e 6 - 2 and ta b l e 6 - 3 . the power modes allow a design to easily provide required functional ity and processing power while simultaneously minimizing power consumption and maximizing battery life in low-power and portable devices. psoc 3 power modes, in order of decreasing power consumption are: ? active ? alternate active ? sleep ? hibernate active is the main processing mode. its functionality is configurable. each power contro llable subsystem is enabled or disabled by using separate power configuration template registers. in alte rnate active mode, fewer subsystems are enabled, reducing power. in sleep mode most resources are disabled regardless of the template settings. sleep mode is optimized to provide timed sleep intervals and rtc functionality. the lowest power mode is hibernate, which retains register and sram state, but no clocks, and allows wakeup only from i/o pins. figure 6-5 illustrates the allowable transitions between power modes. sleep and hibernat e modes should not be entered until all v ddio supplies are at valid voltage levels. . table 6-2. power modes power modes description entry condition wakeup source active clocks regulator active primary mode of operation, all periph- erals available (programmable) wakeup, reset, manual register entry any interrupt any (programmable) all regulators available. digital and analog regulators can be disabled if external regulation used. alternate active similar to active mode, and is typically configured to have fewer peripherals active to reduce power. one possible configuration is to use the udbs for processing, with the cpu turned off manual register entry any interrupt any (programmable) all regulators available. digital and analog regulators can be disabled if external regulation used. sleep all subsystems automatically disabled manual register entry comparator, picu, i 2 c, rtc, ctw, lvd ilo/khzeco both digital and analog regulators buzzed. digital and analog regulators can be disabled if external regulation used. hibernate all subsystems automatically disabled lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled configuration and memory contents retained manual register entry picu ? only hibernate regulator active. table 6-3. power modes wakeup time and power consumption sleep modes wakeup time current (typ) code execution digital resources analog resources clock sources available wakeup sources reset sources active ? 1.2 ma [16] yes all all all ? all alternate active ??user defined all all all ? all sleep <15 s 1 a no i 2 c comparator ilo/khzeco comparator, picu, i 2 c, rtc, ctw, lvd xres, lvd, wdr hibernate <100 s 200 na no none none none picu xres note 16. bus clock off. execute fr om cache at 6 mhz. see table 11-2 on page 68.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 32 of 131 figure 6-5. power mode transitions 6.2.1.1 active mode active mode is the primary oper ating mode of the device. when in active mode, the active configuration template bits control which available resources are enabled or disabled. when a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. user firmware can dynamically control subsystem power by setting and clearing bits in the active configuration template. the cpu can disable itself, in which case the cpu is automatically reenabled at the next wakeup event. when a wakeup event occurs, the global mode is always returned to active, and the cpu is automatically enabled, regardless of its template setting s. active mode is the default global power mode upon boot. 6.2.1.2 alternate active mode alternate active mode is very sim ilar to active mode. in alternate active mode, fewer subsystems are enabled, to reduce power consumption. one possible configuration is to turn off the cpu and flash, and run peripherals at full speed. 6.2.1.3 sleep mode sleep mode reduces power consumption when a resume time of 15 s is acceptable. the wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode. 6.2.1.4 hibernate mode in hibernate mode nearly all of the internal functions are disabled. internal voltages are reduced to the minimal level to keep vital systems alive. config uration state is preserved in hibernate mode and sram memory is retained. gpios configured as digital outputs maintain their previous values and external gpio pin interrupt settings are preserved. the device can only return from hibernate mode in response to an external i/o interrupt. the resume time from hibernate mode is less than 100 s. to achieve an extremely low current, the hibernate regulator has limited capacity. this limits the frequency of any signal present on the input pins - no gpio should toggle at a rate greater than 10 khz while in hibernate mode. if pins must be toggled at a high rate while in a low power mode, use sleep mode instead. 6.2.1.5 wakeup events wakeup events are configurable and can come from an interrupt or device reset. a wakeup event restores the system to active mode. firmware enabled interrupt sources include internally generated interrupts, power super visor, central timewheel, and i/o interrupts. internal interrupt sources can come from a variety of peripherals, such as analog comparators and udbs. the central timewheel provides periodic interrupts to allow the system to wake up, poll periphe rals, or perform real-time functions. reset event sources include the external reset i/o pin (xres), wdt, and precision reset (pres). 6.2.2 boost converter applications that use a supply voltage of less than 1.71 v, such as solar or single cell battery supplies, may use the on-chip boost converter. the boost converter may also be used in any system that requires a higher operating voltage than the supply provides. for instance, this includes driving 5.0 v lcd glass in a 3.3 v system. the boost converter accept s an input voltage as low as 0.5 v. with one low cost inductor it produces a selectable output voltage sourcing enough current to operate the psoc and other on-board components. the boost converter accepts an input voltage vbat from 0.5 v to 3.6 v, and can start up with vbat as low as 0.5 v. the converter provides a user configurable output voltage of 1.8 to 5.0 v (vboost). vbat is typically less than vboost; if vbat is greater than or equal to vboost, then vboost will be the same as vbat. the block can deliver up to 50 ma (iboost) depending on configuration. four pins are associated with the boost converter: vbat, vssb, vboost, and ind. the boosted ou tput voltage is sensed at the vboost pin and must be connected directly to the chip?s supply inputs. an inductor is connec ted between the vbat and ind pins. you can optimize the inductor value to increase the boost converter efficiency based on input voltage, output voltage, current and switching frequency. the external schottky diode shown in figure 6-6 is required only in cases when vboost > 3.6 v. figure 6-6. application for boost converter the switching frequency can be set to 400 khz or 32 khz, to optimize efficiency and component cost. the 400 khz frequency is generated using an oscillator in the boost converter block. the 32 khz frequency is derived from the 32 khz external crystal active manual hibernate alternate active sleep psoc vboost ind vbat vssb vssd vdda vddd vssa 22 f 0. 1 f 22 f 10 h optional schottky diode only required vboost > 3.6 v vddio smp
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 33 of 131 oscillator (khzeco) block. the 32 khz frequency is primarily intended for boost standby mode. at 400 khz vboost is limited to 4 vbat. the boost converter can be operated in two different modes: active and standby. active mode is the normal mode of operation where the boost regulator active ly generates a regulated output voltage. in standby mode, most boost functions are disabled, thus reducing power consumpt ion of the boost circuit. the converter can be configured to provide low-power, low-current regulation in the standby mode. the external 32 khz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. this is calle d automatic thump mode (atm). the boost typically draws 200 a in active mode and 12 a in standby mode. the boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. ta b l e 6 - 4 lists the boost power modes available in different chip power modes. if the boost converter is not used in a given application, tie the vbat, vssb, and vboost pins to ground and leav e the ind pin unconnected. 6.3 reset cy8c36 has multiple internal and external reset sources available. the reset sources are: ? power source monitoring ? the analog and digital power voltages, vdda, vddd, vcca, and vccd are monitored in several different modes during power up, active mode, and sleep mode (buzzing). if any of the voltages goes outside predetermined ranges then a rese t is generated. the monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. ? external ? the device can be reset from an external source by pulling the reset pin (xres ) low. the xres pin includes an internal pull-up to vddio1. vddd, vdda, and vddio1 must all have voltage applied before the part comes out of reset. ? watchdog timer ? a watchdog timer monitors the execution of instructions by the processor. if the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset. ? software ? the device can be reset under program control. figure 6-7. resets the term device reset indicates that the processor as well as analog and digital peripherals and registers are reset. a reset status register shows some of the resets or power voltage monitoring interrupts. the program may examine this register to detect and report certain exceptio n conditions. this register is cleared after a power-on reset. for details see the technical reference manual. 6.3.1 reset sources 6.3.1.1 power voltage level monitors ? ipor ? initial por at initial power on, ipor monitors the power voltages v ddd , v dda , v ccd and v cca . the trip level is not precise. it is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. the monitor generates a reset pulse that is at least 1 50 ns wide. it may be much wider if one or more of the voltages ramps up slowly. if after the ipor triggers either v ddx drops back below the trigger point, in a non-monotonic fashion, it must remain below that point for at least 10 s. th e hysteresis of the ipor trigger point is typically 100 mv. after boot, the ipor circuit is disabled and voltage supervision is handed off to the precise low-voltage reset (pres) circuit. ? pres ? precise low voltage reset this circuit monitors the outputs of the analog and digital internal regulators after power up. the regulator outputs are compared to a precise reference voltage. the response to a pres trip is identica l to an ipor reset. after pres has been deasserted, at least 10 s must elapse before it can be reasserted. in normal operating mode, the program cannot disable the digital pres circuit. the analog regulator can be disabled, which also disables the analog portion of the pres. the pres circuit is disabled automatica lly during sleep and hibernate table 6-4. chip and boost power modes compatibility chip power modes boost power modes chip ? active mode boost can be operated in either active or standby mode. chip ? sleep mode boost can be operated in either active or standby mode. however, it is recom- mended to operate boost in standby mode for low-power consumption chip ? hibernate mode boost can only be operated in active mode. however, it is recommended not to use boost in chip hibernate mode due to high current consumption in boost active mode reset controller watchdog timer external reset power voltage level monitors software reset register vddd vdda reset pin system reset processor interrupt
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 34 of 131 modes, with one exception: during sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. at these times the pres circuit is also buzzed to allow periodic voltage monitoring. ? alvi, dlvi, ahvi ? analog/digital low voltage interrupt, analog high voltage interrupt interrupt circuits are available to detect when vdda and vddd go outside a voltage range. for ahvi, vdda is compared to a fixed trip level. for alvi and dlvi, vdda and vddd are compared to trip levels that are programmable, as listed in table 6-5 . alvi and dlvi can also be configured to generate a device reset instead of an interrupt. the monitors are disabled until after ipor. during sleep mode these circuits are periodically acti vated (buzzed). if an interrupt occurs during buzzing then the system first enters its wake up sequence. the interrupt is then recognized and may be serviced. the buzz frequency is adjustable, and should be set to be less than the minimum time that any voltage is expected to be out of range. for details on how to adjust the buzz frequency, see the trm. 6.3.1.2 other reset sources ? xres ? external reset psoc 3 has either a single gpio pin that is configured as an external reset or a dedicated xres pin. either the dedicated xres pin or the gpio pin, if conf igured, holds the part in reset while held active (low). the response to an xres is the same as to an ipor reset. after xres has been deasserted, at least 10 s must elapse before it can be reasserted. the external reset is active low. it includes an internal pull-up resistor. xres is active during sleep and hibernate modes. ? sres ? software reset a reset can be commanded under program control by setting a bit in the software reset regist er. this is done either directly by the program or indirectly by dma access. the response to a sres is the same as after an ipor reset. another register bit exists to disable this function. ? wres ? watchdog timer reset the watchdog reset detects when the software program is no longer being executed correctly. to indicate to the watchdog timer that it is running correctly , the program must periodically reset the timer. if the timer is not reset before a user-specified amount of time, then a reset is generated. note ipor disables the watchdog function. the program must enable the watchdog function at an appropriate point in the code by setting a register bit. wh en this bit is set, it cannot be cleared again except by an ipor power on reset event. 6.4 i/o system and routing psoc i/os are extremely flexible. every gpio has analog and digital i/o capability. all i/os have a large number of drive modes, which are set at por. psoc also provides up to four individual i/o voltage domains through the vddio pins. there are two types of i/o pins on every device; those with usb provide a third type. both general purpose i/o (gpio) and special i/o (sio) provide similar digital functionality. the primary differences are their analog capability and drive strength. devices that include usb also provide two usbio pins that support specific usb functionality as well as limited gpio capability. all i/o pins are available for use as digital inputs and outputs for both the cpu and digital peripherals. in addition, all i/o pins can generate an interrupt. the flexible and advanced capabilities of the psoc i/o, combined with any signal to any pin routability, greatly simplify circuit design and board layout. all gpio pins can be used for analog input, capsense [17] , and lcd segment drive, while sio pins are used for voltages in excess of v dda and for programmable output voltages. ? features supported by both gpio and sio: ? user programmable port reset state ? separate i/o supplies and voltages for up to four groups of i/o ? digital peripherals use dsi to connect the pins ? input or output or both for cpu and dma ? eight drive modes ? every pin can be an interrupt source configured as rising edge, falling edge or both edges. if required, level sensitive interrupts are supported through the dsi ? dedicated port interrupt vector for each port ? slew rate controlled digital output drive mode ? access port control and configurat ion registers on either port basis or pin basis ? separate port read (ps) and writ e (dr) data registers to avoid read modify write errors ? special functionality on a pin by pin basis ? additional features only provided on the gpio pins: ? lcd segment drive on lcd equipped devices ? capsense [17] ? analog input and output capability ? continuous 100 a clamp current capability ? standard drive strength down to 1.7 v ? additional features only provided on sio pins: ? higher drive strength than gpio ? hot swap capability (5 v tolerance at any operating v dd ) ? programmable and regulated high input and output drive levels down to 1.2 v ? no analog input, capsense, or lcd capability ? over voltage tolerance up to 5.5 v ? sio can act as a general purpose analog comparator ? usbio features: ? full speed usb 2.0 compliant i/o ? highest drive strength for general purpose use ? input, output, or both for cpu and dma ? input, output, or both for digital peripherals ? digital output (cmos) drive mode table 6-5. analog/digital low voltage interrupt, analog high voltage interrupt interrupt supply normal voltage range available trip settings dlvi vddd 1.71 v?5.5 v 1.70 v?5.45 v in 250 mv increments alvi vdda 1.71 v?5.5 v 1.70 v?5.45 v in 250 mv increments ahvi vdda 1.71 v?5.5 v 5.75 v
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 35 of 131 figure 6-8. gpio block diagram note 17. gpios with opamp outputs are not recommended for use with capsense drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw lcd logic & mux prt[x]dm1 prt[x]dm2 prt[x]lcd_en prt[x]lcd_com_seg analog analog mux analog global digital system output 0 1 prt[x]byp prt[x]bie bidirectional control capsense global control switches pin interrupt signal digital system input prt[x]ps prt[x]ctl input buffer disable display data interrupt logic picu[x]inttype[y] picu[x]intstat vddio vddio vddio slew cntl lcd bias bus 5 prt[x]amux prt[x]ag 1 caps[x]cfg1 oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat naming convention ?x? = port number ?y? = pin number 0 1 0 1
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 36 of 131 figure 6-9. sio input/output block diagram figure 6-10. usbio block diagram drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw prt[x]dm1 prt[x]dm2 digital system output 0 1 prt[x]byp prt[x]bie bidirectional control pin interrupt signal digital system input prt[x]ps input buffer disable interrupt logic picu[x]inttype[y] picu[x]intstat slew cntl oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat prt[x]sio_diff buffer thresholds driver vhigh prt[x]sio_cfg prt[x]sio_hyst_en naming convention ?x? = port number ?y? = pin number reference level reference level drive logic prt[15]dr1[7,6] pin digital output path digital input path digital system output 0 1 prt[15]byp pin interrupt signal digital system input usbio_cr1[0,1] interrupt logic picu[15]inttype[y] picu[15]intstat in prt[15]dbl_sync_in picu[15]intstat naming convention ?y? = pin number vddd vddd vddd 5 k 1.5 k d+ pin only prt[15]dm1[6] usbio_cr1[5] usb or i/o d+ 1.5 k d+ 5 k d+ open drain prt[15]sync_out usb sie control for usb mode usb receiver circuitry vddd prt[15]ps[6,7] usbio_cr1[2] d- 5 k prt[15]dm1[7] d- open drain prt[15]dm0[6] prt[15]dm0[7]
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 37 of 131 6.4.1 drive modes each gpio and sio pin is individually configurab le into one of the eight drive modes listed in ta b l e 6 - 6 . three configuration bits are used for each pin (dm[2:0]) and set in the prtxdm[2:0] registers. figure 6-11 depicts a simplified pin view based on each of the eight drive modes. ta b l e 6 - 6 shows the i/o pin?s drive state based on the port data regi ster value or digital array signal if bypass mode is selected. note that the actual i/o pin vo ltage is determined by a combination of th e selected drive mode and the load at the pi n. for example, if a gpio pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. if the same gpio pin is externally tied to ground then the voltage unmeasured at the pin is a low lo gic state. figure 6-11. drive mode table 6-6. drive modes diagram drive mode prtxdm2 prtxdm1 prtxdm0 prtxdr = 1 prtxdr = 0 0 high impedance analog 0 0 0 high z high z 1 high impedance digital 0 0 1 high z high z 2 resistive pull-up [18] 0 1 0 res high (5k) strong low 3 resistive pull-down [18] 0 1 1 strong high res low (5k) 4 open drain, drives low 1 0 0 high z strong low 5 open drain, drive high 1 0 1 strong high high z 6 strong drive 1 1 0 strong high strong low 7 resistive pull-up and pull-down [18] 1 1 1 res high (5k) res low (5k) high impedance analog ps dr ps dr ps dr 0. high impedance digital 1. resistive pull-up 2. resistive pull-down 3. open drain , drives low 4. open drain , drives high 5. strong drive 6. resistive pull-up and pull-down 7. vddio pin pin pin vddio pin pin pin pin pin ps dr ps dr ps dr ps dr ps dr vddio vddio vddio note 18. resistive pull-up and pull-down are not avai lable with sio in regulated output mode.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 38 of 131 the usbio pins (p15[7] and p15[6]), when enabled for i/o mode, have limited drive mode control. the drive mode is set using the prt15.dm0[7, 6] register. a resistive pull option is also avail able at the usbio pins, which can be enabled using the prt15.dm1 [7, 6] register. when enabled for usb mode, the drive mode control has no impact on the configuration of the usb pins. unlike the g pio and sio configurations, the port wide configuration registers do not configure the usb drive mode bits. table 6-7 shows the drive mode configuration for the usbio pins. ? high impedance analog the default reset state with both the output driver and digital input buffer turned off. this prevents any current from flowing in the i/o?s digital input buffer due to a floating voltage. this state is recommended for pins that are floating or that support an analog voltage. high impedance analog pins do not provide digital input functionality. to achieve the lowest chip current in sleep modes, all i/os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the psoc device or by external circuitry. ? high impedance digital the input buffer is enabled for digital signal input. this is the standard high impedance (hiz) state recommended for digital inputs. ? resistive pull-up or resistive pull-down resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. pins can be used for di gital input and output in these modes. interfacing to mechani cal switches is a common application for these modes. resistive pull-up and pull-down are not available with sio in regulated output mode. ? open drain, drives high a nd open drain, drives low open drain modes provide high impedance in one of the data states and strong drive in the other. pins can be used for digital input and output in these modes. a common application for these modes is driving the i 2 c bus signal lines. ? strong drive provides a strong cmos output drive in either high or low state. this is the standard out put mode for pins. strong drive mode pins must not be used as inputs under normal circumstances. this mode is often used to drive digital output signals or external fets. ? resistive pull-up and pull-down similar to the resistive pull- up and resistive pull-down modes except the pin is always in series with a resistor. the high data state is pull-up while the low data state is pull-down. this mode is most often used when other signals that may cause shorts can drive the bus. resistive pull-up and pull-down are not available with sio in regulated output mode. 6.4.2 pin registers registers to configure and interact with pins come in two forms that may be used interchangeably. all i/o registers are available in the standard port form, where each bit of the register correspond s to one of the port pins. this register form is efficient for quickly reconfiguring multiple port pins at the same time. i/o registers are also available in pin form, which combines the eight most commonly used port regist er bits into a single register for each pin. this enables very fast configuration changes to individual pins with a single register write. 6.4.3 bidirectional mode high speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode su ch as strong drive (set using prtdm[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. the bidirectional capability is useful for processor busses and communications interfaces such as the spi slave miso pin that requires dynamic hardware control of the output buffer. the auxiliary control bus routes up to 16 udb or digital peripheral generated output enable signals to one or more pins. 6.4.4 slew rate limited mode gpio and sio pins have fast and slow output slew rate options for strong and open drain drive m odes, not resistive drive modes. because it results in reduced emi, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 mhz. the fast slew rate is for signals between 1 mhz and 33 mhz. the slew rate is individually configurable for each pin, and is set by the prtslw registers. table 6-7. usbio drive modes (p15[7] and p15[6]) prt15.dm1[7,6] pull up enable prt15.dm0[7,6] drive mode enable prt15.dr[7,6] = 1 prt15.dr[7,6] = 0 description 0 0 high z strong low open drain, strong low 0 1 strong high strong low strong outputs 1 0 res high (5k) strong low resistive pull up, strong low 1 1 strong high strong low strong outputs
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 39 of 131 6.4.5 pin interrupts all gpio and sio pins are able to generate interrupts to the system. all eight pins in each po rt interface to their own port interrupt control unit (picu) a nd associated in terrupt vector. each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to ?1? and an interrupt request is sent to the interrupt controller. each picu has its own interrupt vector in the interrupt controll er and the pin status register providing easy determination of the interrupt source down to the pin level. port pin interrupts remain active in all sleep modes allowing the psoc device to wake from an externally generated interrupt. while level sensitive interrupts are not directly supported; universal digital blocks (udb) prov ide this functionality to the system when needed. 6.4.6 input buffer mode gpio and sio input buffers can be configured at the port level for the default cmos input thresholds or the optional lvttl input thresholds. all input buffers incorporate schmitt triggers for input hysteresis. additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 i/o power supplies up to four i/o pin power supplie s are provided depending on the device and package. each i/o supply must be less than or equal to the voltage on the chip?s analog (v dda ) pin. this feature allows users to provide different i/o voltage levels for different pins on the device. refer to the spec ific device package pinout to determine vddio capability for a given port and pin. the sio port pins support an additional regulated high output capability, as described in adjustable output level . 6.4.8 analog connections these connections apply only to gpio pins. all gpio pins may be used as analog inputs or outputs. the analog voltage present on the pin must not exceed the vddio supply voltage to which the gpio belongs. each gpio may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as adc or comparators. in addition, select pins provide direct connections to specific analog features such as the high current dacs or uncommitted opamps. 6.4.9 capsense this section applies only to gp io pins. all gpio pins may be used to create capsense buttons and sliders [19] . see the ?capsense? section on page 60 fo r more information. 6.4.10 lcd segment drive this section applies only to gp io pins. all gpio pins may be used to generate segment and common drive signals for direct glass drive of lcd glass. see the ?lcd direct drive? section on page 59 for details. 6.4.11 adjustable output level this section applies only to sio pins. sio port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the sio?s respective vddio. sio pins are individually configurable to output either the standard vddio level or the regulated output, which is based on an internally generated reference. typically a voltage dac (vdac) is used to generate the reference (see figure 6-12 ). the ?dac? section on page 60 has more details on vdac use and reference routing to the sio pins. resistive pull-up and pull-down drive modes are not available with sio in regulated output mode. 6.4.12 adjustable input level this section applies only to sio pins. sio pins by default support the standard cmos and lvttl input levels but also support a differential mode with program mable levels. sio pins are grouped into pairs. each pair sh ares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from vddio. the reference sets the pins voltage threshold for a high logic level (see figure 6-12 ). available input thresholds are: ? 0.5 ?? vddio ? 0.4 ?? vddio ? 0.5 ?? v ref ? v ref typically a voltage dac (vdac) generates the v ref reference. ?dac? section on page 60 has more details on vdac use and reference routing to the sio pins. note 19. gpios with opamp outputs are not recommended for use with capsense
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 40 of 131 figure 6-12. sio reference for input and output 6.4.13 sio as comparator this section applies only to sio pins. the adjustable input level feature of the sios as explained in the adjustable input level section can be used to construct a comparator. the threshold for the comparator is provided by the sio's reference generator. the reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. note that a pair of sio pins share the same threshold. the digital input path in figure 6-9 on page 36 illustrates this functionality. in the figure, ?refe rence level? is the analog signal routed through the analog glob al. the hysteresis feature can also be enabled for the input buffer of the sio, which increases noise immunity for the comparator. 6.4.14 hot swap this section applies only to sio pins. sio pins support ?hot swap? capability to plug into an application without loading the signals that are connected to the sio pins even when no power is applied to the psoc device. this allows the unpowered psoc to maintain a high impedance load to the external device while also preventing the psoc from being powered through a sio pin?s protection diode. powering the device up or down while connected to an operational i2c bus may cause tr ansient states on the sio pins. the overall i2c bus design should take this into account. 6.4.15 over voltage tolerance all i/o pins provide an over vo ltage tolerance feature at any operating v dd . ? there are no current limitations for the sio pins as they present a high impedance load to the external circuit where vddio < v in < 5.5 v. ? the gpio pins must be limited to 100 a using a current limiting resistor. gpio pins clamp the pi n voltage to approximately one diode above the vddio supply where vddio < v in < v dda . ? in case of a gpio pin configured for analog input/output, the analog voltage on the pin must not exceed the vddio supply voltage to which the gpio belongs. a common application for this feat ure is connection to a bus such as i 2 c where different devices are running from different supply voltages. in the i 2 c case, the psoc chip is configured into the open drain, drives low mode for the sio pin. this allows an external pull-up to pull the i 2 c bus voltage above the psoc pin supply. for example, the psoc chip could operate at 1.8 v, and an external device could run from 5 v. note that the sio pin?s v ih and v il levels are determined by the associated vddio supply pin. the sio pin must be in one of the following modes: 0 (high impedance analog), 1 (high impedance digital), or 4 (open drain drives low). see figure 6-11 for details. absolute maximum ratings for the device must be observed for all i/o pins. 6.4.16 reset configuration while reset is active all i/os are reset to and held in the high impedance analog state. after rese t is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. to ensure correct reset operation, the port reset configuration data is stored in special nonvolatile regi sters. the stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.17 low-power functionality in all low-power modes the i/o pins retain their state until the part is awakened and changed or reset. to awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low-power modes. 6.4.18 special pin functionality some pins on the device include additional special functionality in addition to their gpio or sio functionality. the specific special function pins are listed in pinouts on page 5. the special features are: ? digital ? 4- to 25-mhz crystal oscillator ? 32.768-khz crystal oscillator ? wake from sleep on i 2 c address match. any pin can be used for i 2 c if wake from sleep is not required. ? jtag interface pins ? swd interface pins ? swv interface pins ? external reset ? analog ? opamp inputs and outputs pin drive logic driver vhigh reference generator sio_ref digital input digital output input path output path vinref voutref
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 41 of 131 ? high current idac outputs ? external reference inputs 6.4.19 jtag boundary scan the device supports standard jtag boundary scan chains on all i/o pins for board level test. 7. digital subsystem the digital programmable system creates applicat ion specific combinations of both standard and advanced digital peripherals and custom logic functions. these peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and ip security. the features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. you do not need to interact directly with the programmable digital system at the hardware and regi ster level. psoc creator provides a high level schematic capture graphical interface to automatically place and route resources similar to plds. the main components of the digital programmable system are: ? universal digital blocks (udb) ? these form the core functionality of the digital pr ogrammable system. udbs are a collection of uncommitted logic (pld) and structural logic (datapath) optimized to create all common embedded peripherals and customized functio nality that are application or design specific. ? universal digital block array ? udb blocks are arrayed within a matrix of programmable interconnect. the udb array structure is homogeneous and allows for flexible mapping of digital functions onto the array. the array supports extensive and flexible routing interconnects between udbs and the digital system interconnect. ? digital system interconnect (dsi) ? digital signals from universal digital blocks (udbs), fixed function peripherals, i/o pins, interrupts, dma, and ot her system core signals are attached to the digital system interconnect to implement full featured device connectivity. the dsi allows any digital function to any pin or other feature routability when used with the universal digital block array. figure 7-1. cy8c36 digital programmable architecture 7.1 example peripherals the flexibility of the cy8c36 fa mily?s universal digital blocks (udbs) and analog blocks allow the user to create a wide range of components (peripherals). the most common peripherals were built and characterized by cypress and are shown in the psoc creator component catalog, however, users may also create their own custom components using psoc creator. using psoc creator, users may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. the number of components available through psoc creator is too numerous to list in the data sheet, and the list is always growing. an example of a component available for use in cy8c36 family, but, not explicitly called out in this data sheet is the uart component. 7.1.1 example digital components the following is a sample of the digital components available in psoc creator for the cy8c36 family. the exact amount of hardware resources (udbs, rout ing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? communications ? i 2 c ? uart ? spi ? functions ? emif ? pwms ? timers ? counters ? logic ? not ? or ? xor ? and 7.1.2 example analog components the following is a sample of the analog components available in psoc creator for the cy8c36 family. the exact amount of hardware resources (sc/ct blo cks, routing, ra m, flash) used by a component varies with t he features selected in psoc creator for the component. ? amplifiers ? tia ? pga ? opamp ? adc ? delta-sigma ? dacs ? current ? voltage ? pwm ? comparators ? mixers io port digital core system and fixed function peripherals udb array udb array io port io port io port dsi routing interface dsi routing interface digital core system and fixed function peripherals udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 42 of 131 7.1.3 example system function components the following is a sample of the system function components available in psoc creator for the cy8c36 family. the exact amount of hardware resources (udbs, dfb taps, sc/ct blocks, routing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? capsense ? lcd drive ? lcd control ? filters 7.1.4 designing with psoc creator 7.1.4.1 more than a typical ide a successful design tool allows for the rapid development and deployment of both simple and complex designs. it reduces or eliminates any learning curve. it makes the integration of a new design into the production stream straightforward. psoc creator is that design tool. psoc creator is a full featur ed integrated development environment (ide) for hardware and software design. it is optimized specifically for psoc devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. this unique combination of tools makes psoc creator the most flexible embedded design platform available. graphical design entry simplifies the task of configuring a particular part. you can select th e required functionality from an extensive catalog of components an d place it in your design. all components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. psoc creator automatical ly configures cloc ks and routes the i/o to the selected pins and then generates apis to give the application complete control over the hardware. changing the psoc device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. at any stage of development you are free to change the hardware configuration and even the target processor. to retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. you also have the ability to chan ge the c compiler and evaluate an alternative. components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. switching compilers is as easy as editing the from the project options and rebuilding the application with no errors from the generated apis or boot code. figure 7-2. psoc creator framework
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 43 of 131 7.1.4.2 component catalog figure 7-3. component catalog the component catalog is a repository of reusable design elements that select device functionality and customize your psoc device. it is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and pwms, plus analog components such as adc, dacs, and filters, and communication protocols, such as i 2 c, usb, and can. see example peripherals on page 41 for more details about available peripherals. all content is fu lly characterized and carefully documented in data sheets with code examples, ac/dc specifications, and user code ready apis. 7.1.4.3 design reuse the symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. just draw a symbol and associate that symbol with your proven design. psoc creator allows fo r the placement of the new symbol anywhere in the component catalog along with the content provided by cypress. you can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation. 7.1.4.4 software development figure 7-4. code editor anchoring the tool is a modern, highly customizable user interface. it includes project m anagement and integrated editors for c and assembler source code, as well the design entry tools. project build control leverages compiler technology from top commercial vendors such as arm ? limited, keil?, and codesourcery (gnu). free versions of keil c51 and gnu c compiler (gcc) for arm, with no rest rictions on code size or end product distribution, are includ ed with the tool distribution. upgrading to more optimizing compilers is a snap with support for the professional keil c51 product and arm realview? compiler. 7.1.4.5 nonintrusive debugging figure 7-5. psoc creator debugger with jtag (4-wire) and swd (2-wire) debug connectivity available on all devices, the psoc creator debugger offers full control over the target device with minimum intrusion. breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows?register, locals, watch, call stack, memory and peripherals?make for an unparalleled level of visibility into the system.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 44 of 131 psoc creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. all steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. 7.2 universal digital block the universal digital block (udb ) represents an evolutionary step to the next generation of psoc embedded digital peripheral functionality. the architecture in first generation psoc digital blocks provides coarse progra mmability in which a few fixed functions with a small number of options are available. the new udb architecture is the optima l balance between configuration granularity and efficient implementation. a cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. to achieve this, udbs consist of a combination of uncommitted logic (pld), structured logic (dat apath), and a flexible routing scheme to provide interconnect between these elements, i/o connections, and other peripherals. udb functionality ranges from simple self contained functions that are implemented in one udb, or even a portion of a udb (unused resources are available for other functions), to more complex functions that require multiple udbs. examples of basic functions are timers, counters, crc generators, pwms, dead band generators, and communications functions, such as uarts, spi, and i 2 c. also, the pld blocks and conn ectivity provide fu ll featured general purpose programmable logic within the limits of the available resources. figure 7-6. udb block diagram the main component blocks of the udb are: ? pld blocks ? there are two sma ll plds per udb. these blocks take inputs from the routing array and form registered or combinational sum-of-products logic. plds are used to implement state machines, state bits, and combinational logic equations. pld configuration is automatically generated from graphical primitives. ? datapath module ? this 8-bit wide datapath contains structured logic to implement a dynamically configurable alu, a variety of compare configurations and co ndition generation. this block also contains input/output fifos, which are the primary parallel data interface between the cpu/dma system and the udb. ? status and control module ? the prim ary role of this block is to provide a way for cpu firmware to interact and synchronize with udb operation. ? clock and reset module ? this block provides the udb clocks and reset selection and control. 7.2.1 pld module the primary purpose of the pld blocks is to implement logic expressions, state machines, sequencers, lookup tables, and decoders. in the simple st use model, consider the pld blocks as a standalone resource onto which general purpose rtl is synthesized and mapped. the more common and efficient use model is to create digital func tions from a combination of pld and datapath blocks, where the pld implements only the random logic and state portion of the function while the datapath (alu) implements the more structured elements. figure 7-7. pld 12c4 structure one 12c4 pld block is shown in figure 7-7 . this pld has 12 inputs, which feed across eight product terms. each product term (and function) can be from 1 to 12 inputs wide, and in a given product term, the true (t) or complement (c) of each input can be selected. the product terms are summed (or function) to create the pld outputs. a sum can be from 1 to 8 product terms wide. the 'c' in 12c4 indicates that the width of the or gate (in this case 8) is constant across all outputs (rather than variable as in a 22v10 device). this pla like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. there are two 12c4 plds in each udb. pld 12c4 (8 pts) pld 12c4 (8 pts) datapath clock and reset control routing channel datapath chaining pld chaining status and control pt0 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc pt1 pt2 pt3 pt4 pt5 pt6 pt7 tttttttt tttttttt tttttttt tttttttt and array or array mc0 mc1 mc2 out0 out1 out2 out3 mc3 selin (carry in) selout (carry out)
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 45 of 131 7.2.2 datapath module the datapath contains an 8-bit single cycle alu, with associated compare and condition generation logi c. this datapath block is optimized to implement embedded functions, such as timers, co unters, integrators, pwms, prs, crc, shifters and dead band generators and many others. figure 7-8. datapath top level 7.2.2.1 working registers the datapath contains six primary working registers, which are accessed by cpu firmware or dma during normal operation. 7.2.2.2 dynamic datapath configuration ram dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. this is implemented using the 8-word 16-bit configuration ram, which stores eight unique 16-bit wide configurations. the address input to this ram controls the sequence, and can be routed from any block connected to the udb routing matr ix, most typically pld logic, i/o pins, or from the outputs of this or other datapath blocks. alu the alu performs eight general purpose functions. they are: ? increment ? decrement ? add ? subtract ? logical and ? logical or ? logical xor ? pass, used to pass a value through the alu to the shift register, mask, or another udb register a0 a1 d0 d1 pi alu mask shift data registers output muxes f1 f0 fifos accumulators po a0 a1 d0 d1 output to programmable routing chaining control store ram 8 word x 16 bit parallel input/output (to/from programmable routing) input from programmable routing input muxes to/from next datapath to/from previous datapath datapath control phub system bus r/w access to all registers conditions: 2 compares, 2 zero detect, 2 ones detect overflow detect 6 6 table 7-1. working datapath registers name function description a0 and a1 accumulators these are sources and sinks for the alu and also sources for the compares. d0 and d1 data registers these are sources for the alu and sources for the compares. f0 and f1 fifos these are the primary interface to the system bus. they can be a data source for the data registers and accumulators or they can capture data from the accumulators or alu. each fifo is four bytes deep.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 46 of 131 independent of the alu operation, these functions are available: ? shift left ? shift right ? nibble swap ? bitwise or mask 7.2.2.3 conditionals each datapath has two compar es, with bit masking options. compare operands include the two accumulators and the two data registers in a variety of configurations. other conditions include zero detect, all ones detect, and overflow. these conditions are the primary datapat h outputs, a selection of which can be driven out to the udb routing matrix. conditional computation can use the built in chaining to neighboring udbs to operate on wider data widths without the need to use routing resources. 7.2.2.4 variable msb the most significant bit of an arithmetic and shift function can be programmatically specified. this supports variable width crc and prs functions, and in conjunction with alu output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.5 built in crc/prs the datapath has built in support for single cycle crc computation and prs generation of arbitrary width and arbitrary polynomial. crc/prs functions longer than 8 bits may be implemented in conjunction with pld logic, or built in chaining may be use to extend the func tion into neighboring udbs. 7.2.2.6 input/output fifos each datapath contains two four-byte deep fifos, which can be independently configured as an i nput buffer (system bus writes to the fifo, datapath internal reads the fifo), or an output buffer (datapath internal writes to the fifo, the system bus reads from the fifo). the fifos generat e status that are selectable as datapath outputs and can theref ore be driven to the routing, to interact with sequencer s, interrupts, or dma. figure 7-9. example fifo configurations 7.2.2.7 chaining the datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithm etic, shift, crc/prs functions. 7.2.2.8 time multiplexing in applications that are over sa mpled, or do not need high clock rates, the single alu block in the datapath can be efficiently shared with two sets of register s and condition generators. carry and shift out data from the alu are registered and can be selected as inputs in subsequent cycles. this provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.9 datapath i/o there are six inputs and six outputs that connect the datapath to the routing matrix. inputs fr om the routing provide the configuration for the datapath oper ation to perform in each cycle, and the serial data inputs. inputs can be routed from other udb blocks, other device peripherals, device i/o pins, and so on. the outputs to the routing can be selected from the generated conditions, and the serial data outputs. outputs can be routed to other udb blocks, device per ipherals, interrupt and dma controller, i/o pins, and so on. 7.2.3 status and control module the primary purpose of this circuitry is to coordinate cpu firmware interaction with internal udb operation. figure 7-10. status and control registers the bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of udb processing. the status register is read-only and it allows internal udb state to be read out onto th e system bus directly from internal routing. this allows firm ware to monitor the state of udb processing. each bit of these registers has programmable connections to the routing matr ix and routing connections are made depending on the requirem ents of the application. 7.2.3.1 usage examples as an example of control input, a bit in the control register can be allocated as a function enable bit. there are multiple ways to enable a function. in one method the control bit output would be routed to the clock control block in one or more udbs and serve as a clock enable for the selected udb blocks. a status example is a case where a pld or datapath block generated a condition, such as a ?compare true? condi tion that is captured and latched by the status register and then read (and cleared) by cpu firmware. 7.2.3.2 clock generation each subcomponent block of a udb including the two plds, the datapath, and status and control, has a clock selection and control block. this promotes a fine granularity with respect to allocating clocking resources to udb component blocks and allows unused udb resources to be used by other functions for maximum system efficiency. system bus f0 f1 system bus a0/a1/alu d0/d1 a0/a1/alu system bus f1 a0/a1/alu f0 d0 system bus f1 a0 d1 a1 f0 tx/rx dual capture dual buffer routing channel 8-bit status register (read only) 8-bit control register (write/read) system bus
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 47 of 131 7.3 udb array description figure 7-11 shows an example of a 16-udb array. in addition to the array core, there are a dsi ro uting interfaces at the top and bottom of the array. other interfac es that are not explicitly shown include the system inte rfaces for bus and cl ock distribu tion. the udb array includes multiple horizontal and vertical routing channels each comprised of 96 wires. the wire connections to udbs, at horizontal/vertical inte rsection and at the dsi interface are highly permutable providing ef ficient automatic routing in psoc creator. additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. figure 7-11. digital system interface structure 7.3.1 udb array programmable resources figure 7-12 shows an example of how functions are mapped into a bank of 16 udbs. the primary programmable resources of the udb are two plds, one datapath and one status/control register. these resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to ot her unrelated functions. an example of this is the 8-bit ti mer in the upper left corner of the array. this function only requires one datapath in the udb, and therefore the pld resource s may be allocated to another function. a function such as a quadrature decoder may require more pld logic than one udb can supply and in this case can utilize the unused pld blo cks in the 8-bit timer udb. programmable resources in the udb array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. figure 7-12. function mappin g example in a bank of udbs 7.4 dsi routing interface description the dsi routing interface is a c ontinuation of the horizontal and vertical routing channels at t he top and bottom of the udb array core. it provides general purpose programmable routing between device peripherals, including udbs, i/os, analog peripherals, interrupts, dma and fixed function peripherals. figure 7-13 illustrates the concept of the digital system interconnect, which connects t he udb array routing matrix with other device peripherals. any digital core or fixed function peripheral that needs programmable routing is connected to this interface. signals in this category include: ? interrupt requests from all digital peripherals in the system. ? dma requests from all digital peripherals in the system. ? digital peripheral data signals that need flexible routing to i/os. ? digital peripheral data signals that need connections to udbs. ? connections to the interrupt and dma controllers. ? connection to i/o pins. ? connection to analog system digital signals. udb udb hv b udb udb hv a udb udb hv b hv a udb udb hv a udb udb hv b udb udb hv a hv b hv b hv a hv b hv a hv a hv b hv a hv b udb udb udb udb system connections system connections udb udb hv b udb udb hv a udb udb hv b hv a udb hv a udb hv b udb hv a hv b udb udb udb udb udb udb uart logic 12-bit pwm i2c slave 8-bit spi 12-bit spi logic 8-bit timer 16-bit pyrs udb 8-bit timer quadrature decoder 16-bit pwm sequencer
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 48 of 131 figure 7-13. digital system interconnect interrupt and dma routing is very flexible in the cy8c36 programmable architecture. in addition to the numerous fixed function peripherals that can gen erate interrupt requests, any data signal in the udb array routing can also be used to generate a request. a single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. figure 7-14 shows the structure of the idmux (interrupt/dma multiplexer). figure 7-14. interrupt and dma processing in the idmux 7.4.1 i/o port routing there are a total of 20 dsi routes to a typical 8-bit i/o port, 16 for data and four for drive strength control. when an i/o pin is connected to the routing, there are two primary connections available, an input and an output. in conjunction with drive strength c ontrol, this can implement a bidirectional i/o pin. a data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. the synchronization clock is the master clock (see figure 6-1 on page 27). normally all inputs from pins are synchronized as this is required if the cpu interacts with the signal or any signal derived from it. asynchronous inputs have rare uses. an example of this is a feed through of combinational pld logic from input pins to output pins. figure 7-15. i/o pin synchronization routing figure 7-16. i/o pin output connectivity there are four more dsi connections to a given i/o port to implement dynamic output enab le control of pins. this connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. the output enable signal is us eful for creating tri-state bidirectional pins and buses. udb array digital system routing i/f digital system routing i/f can interrupt controller i2c io port pins dma controller io port pins del-sig comparators dacs sc/ct blocks global clocks emif global clocks timer counters dma termout (irqs) dma controller interrupt controller fixed function irqs edge detect edge detect irqs udb array fixed function drqs drqs interrupt and dma processing in idmux 0 1 2 3 0 1 2 do di port i pin 0 do pin1 do pin2 do pin3 do pin4 do pin5 do pin6 do pin7 do 8 io data output connections from the udb array digital system interface
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 49 of 131 figure 7-17. i/o pin output enable connectivity 7.5 can the can peripheral is a fully functional can supporting communication baud rates up to 1 mbps. the can controller implements the can2.0a and can2.0b specifications as defined in the bosch specification and conforms to the iso-11898-1 standard. the can protocol was originally designed for automotive applications with a focus on a high level of fault detection. this ensures high communication reliability at a low cost. because of its succe ss in automotive applications, can is used as a standard communication protocol for motion oriented machine control networks (canopen) and factory automation applications (devicenet). the can controller features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller cpu. full config uration support is provided in psoc creator. figure 7-18. can bus system implementation 7.5.1 can features ? can2.0a/b protocol implementation ? iso 11898 compliant ? standard and extended frames with up to 8 bytes of data per frame ? message filter capabilities ? remote transmission request (rtr) support ? programmable bit rate up to 1 mbps ? listen only mode ? sw readable error counter and indicator ? sleep mode: wake the device from sleep with activity on the rx pin ? supports two or three wire interface to external transceiver (tx, rx, and enable). the three-wire interface is compatible with the philips phy; the phy is not included on-chip. the three wires can be routed to any i/o ? enhanced interrupt controller ? can receive and transmit buffers status ? can controller error status including busoff ? receive path ? 16 receive buffers each with its own message filter ? enhanced hardware message filter implementation that covers the id, ide, and rtr ? devicenet addressing support ? multiple receive buffers linkable to build a larger receive message array ? automatic transmission request (rtr) response handler ? lost received message notification ? transmit path ? eight transmit buffers ? programmable transmit priority ? round robin ?fixed priority ? message transmissions abort capability 7.5.2 software tools support can controller configuration in tegrated into psoc creator: ? can configuration walkthrough with bit timing analyzer ? receive filter setup port i pin 0 oe pin1 oe pin2 oe pin3 oe pin4 oe pin5 oe pin6 oe pin7 oe 4 io control signal connections from udb array digital system interface can node 1 psoc can controller can transceiver tx rx en can node 2 can node n can_h can_l can_h can_l can_h can_l can drivers can bus
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 50 of 131 figure 7-19. can controller block diagram txmessage0 txreq txabort txmessage7 txreq txabort txmessage1 txreq txabort txmessage6 txreq txabort priority arbiter rxmessage0 rxmessage15 rxmessage1 rxmessage14 rxmessage handler acceptance code 0 acceptance mask 0 acceptance code 1 acceptance mask 1 acceptance code 14 acceptance mask 14 acceptance code 15 acceptance mask 15 rtr rxmessages 0-15 tx can framer crc generator rx can framer crc check bit timing error detection crc form ack bit stuffing bit error overload arbitration txinterrupt request (if enabled) rxinterrupt request (if enabled) error status error active error passive bus off tx error counter rx error counter errinterrupt request (if enabled) wakeup request rx buffer status rxmessage available tx buffer status txreq pending rx tx
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 51 of 131 7.6 usb psoc includes a dedicated full-speed (12 mbps) usb 2.0 transceiver supporting all four usb transfer types: control, interrupt, bulk, and isochronous. psoc creator provides full configuration support. usb interfaces to hosts through two dedicated usbio pins, which are detailed in the ?i/o system and routing? section on page 34. usb includes the following features: ? eight unidirectional data endpoints ? one bidirectional control endpoint 0 (ep0) ? shared 512-byte buffer for the eight data endpoints ? dedicated 8-byte buffer for ep0 ? three memory modes ? manual memory management with no dma access ? manual memory management with manual dma access ? automatic memory management with automatic dma access ? internal 3.3-v regulator for transceiver ? internal 48-mhz main oscillator mode that auto locks to usb bus clock, requiring no external crystal for usb (usb equipped parts only) ? interrupts on bus and each endpoint event, with device wakeup ? usb reset, suspend, and resume operations ? bus-powered and self-powered modes figure 7-20. usb 7.7 timers, counters, and pwms the timer/counter/pwm peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. as almost all embedded systems use some combination of timers, counters, and pwms. four of them have been included on this psoc device family. additional and more advanced functionality timers, counters, and pwms can also be instantiated in universal digita l blocks (udbs) as required. psoc creator allows you to choose the timer, counter, and pwm features that they require. the tool set utilizes the most optimal resources available. the timer/counter/pwm peripheral can select from multiple clock sources, with input and ou tput signals connected through the dsi routing. dsi routing allows input and output connections to any device pin and any internal digital signal accessible through the dsi. each of the four instances has a compare output, terminal count output ( optional complementary compare output), and programmable interrupt request line. the timer/counter/pwms are configurab le as free running, one shot, or enable input controlled. the peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. the peripheral suppor ts full 16-bit capture. timer/counter/pwm features include: ? 16-bit timer/counter/pwm (down count only) ? selectable clock source ? pwm comparator (configurable for lt, lte, eq, gte, gt) ? period reload on start, reset, and terminal count ? interrupt on terminal count, compare true, or capture ? dynamic counter reads ? timer capture mode ? count while enable signal is asserted mode ? free run mode ? one shot mode (stop at end of period) ? complementary pwm outputs with deadband ? pwm output kill figure 7-21. timer/counter/pwm s i e (serial interface engine) 48 mhz imo arbiter 512 x 8 sram usb i/o d+ d? interrupts system bus external 22 ? resistors timer / counter / pwm 16-bit clock reset enable capture kill irq compare tc / compare!
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 52 of 131 7.8 i 2 c the i 2 c peripheral provides a synchronous two wire interface designed to interface the psoc device with a two wire i 2 c serial communication bus. the bus is compatible with philips ?the i 2 c specification? version 2.1. additional i 2 c interfaces can be instantiated using universal digital blocks (udbs) in psoc creator, as required. to eliminate the need for excessive cpu intervention and overhead, i 2 c specific support is provided for status detection and generation of framing bits. i 2 c operates as a slave, a master, or multimaster (slave and master) [20] . in slave mode, the unit always listens for a start condition to begin sending or receiving data. master mode supplies the ab ility to generate the start and stop conditions and initiate transactions. multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. if ma ster mode is enabled and slave mode is not enabled, the block does not generate interrupts on externally generated start conditions. i 2 c interfaces through dsi routing and allows direct connections to any gpio or sio pins. i 2 c provides hardware address detect of a 7-bit address without cpu intervention. additionally the device can wake from low-power modes on a 7-bit hardw are address match. if wakeup functionality is required, i 2 c pin connections are limited to the two special sets of sio pins. i 2 c features include: ? slave and master, transmitter, and receiver operation ? byte processing for low cpu overhead ? interrupt or polling cpu interface ? support for bus speeds up to 1 mbps ? 7 or 10-bit addressing (10-bit addressing requires firmware support) ? smbus operation (through firmware support ? smbus supported in hardware in udbs) ? 7-bit hardware address compare ? wake from low-power modes on address match data transfers follow the format shown in figure 7-22 . after the start condition (s), a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) - a 'zero' indicates a transmission (write), a 'one' indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start condition (sr) and address another slave without first generat ing a stop condition. various combinations of read/write formats are then possible within such a transfer. figure 7-22. i 2 c complete transfer timing note 20. fixed-block i2c does not support undefined bus conditions. thes e conditions should be avoided, or the udb-based i2c componen t should be used instead. sda scl 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 start condition address r/w ack data ack data ack stop condition
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 53 of 131 7.9 digital filter block some devices in the cy8c36 family of devices have a dedicated hw accelerator block used for digital filtering. the dfb has a dedicated multiplier and accumulator that calculates a 24-bit by 24-bit multiply accumulate in one bus clock cycle. this enables the mapping of a direct form fir filter that approaches a computation rate of one fir tap for each clock cycle. the mcu can implement any of the function s performed by this block, but at a slower rate that consumes mcu bandwidth. the heart of the dfb is a datapa th (dp), which is the numerical calculation unit of the dfb. the dp is a 24-bit fixed-point numerical processor containing a 48-bit multiply and accumulate function (mac), a multi-function alu, sample and coefficient data rams as well as data routing, shifting, holding and rounding functions. in the mac, two 24-bit values can be multiplied and the result added to the 48-bit accumulator in each bus clock cycle. the mac is the only portion of the dp that is wider than 24 bits. all results from the mac are passed on to the alu as 24-bit values representing the high-order 24 bits in the accumulator shifted by one (bits 46:23). the mac assumes an implied binary point after the most significant bit. the dp also contains an optimized alu that supports add, subtract, comparison, threshold, absolute value, squelch, saturation, and other functions. the dp unit is controlled by seven control fields totaling 18 bits coming from the dfb controller. for more in formation see the trm. the psoc creator interface provides a wizard to implement fir and iir digital filters with coefficients for lpf, bpf, hpf, notch and arbitrary shape filters. 64 pairs of data and coefficients are stored. this enables a 64 tap fir filt er or up to 4 16 tap filters of either fir or iir formulation. figure 7-23. dfb application diagram (pwr/gnd not shown) the typical use model is for data to be supplied to the dfb over the system bus from another on-c hip system data source such as an adc. the data typically passes through main memory or is directly transferred from another chip resource through dma. the dfb processes this data and passes the result to another on chip resource such as a dac or main memory through dma on the system bus. data movement in or out of the dfb is typically controlled by the system dma controller but can be moved directly by the mcu. 8. analog subsystem the analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. these blo cks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and ip security. the features of the analog subsystem are outlined her e to provide an overview of capabilities and architecture. ? flexible, configurable analog r outing architecture provided by analog globals, analog mux bus, and analog local buses. ? high resolution delta-sigma adc. ? up to four 8-bit dacs that pr ovide either voltage or current output. ? four comparators with optional connection to configurable lut outputs. ? up to four configurable switched capacitor/continuous time (sc/ct) blocks for functions that include opamp, unity gain buffer, programmable gain amplifier, transimpedance amplifier, and mixer. ? up to four opamps for internal use and connection to gpio that can be used as high current output buffers. ? capsense subsystem to enabl e capacitive touch sensing. ? precision reference for generating an accurate analog voltage for internal analog blocks. digital filter block write_data read_data system bus dma ctrl data source (phub) data dest (phub) addr digital routing busclk dma request
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 54 of 131 figure 8-1. analog subsystem block diagram the psoc creator software program provides a user friendly interface to configure the analog connections between the gpio and various analog resources and connections from one analog resource to another. psoc creator also provides component libraries that allow you to conf igure the various analog blocks to perform application specific functions (pga, transimpedance amplifier, voltage dac, current dac, and so on). the tool also generates api interface libraries t hat allow you to write firmware that allows the communication between the analog peripheral and cpu/memory. 8.1 analog routing the cy8c36 family of devices has a flexible analog routing architecture that provides the capability to connect gpios and different analog blocks, and also route signals between different analog blocks. one of the strong points of this flexible routing architecture is that it allows dy namic routing of input and output connections to the di fferent analog blocks. for information on how to make pin selections for optimal analog routing, refer to the application note, an58304 - psoc? 3 and psoc? 5 - pin selection for analog designs. 8.1.1 features ? flexible, configurable analog routing architecture ? 16 analog globals (ag) and two analog mux buses (amuxbus) to connect gpios and the analog blocks ? each gpio is connected to one analog global and one analog mux bus ? eight analog local buses (abus) to route signals between the different analog blocks ? multiplexers and switches for in put and output se lection of the analog blocks 8.1.2 functional description analog globals (ags) and analog mux buses (amuxbus) provide analog connectivity between gpios and the various analog blocks. there are 16 ags in the cy8c36 family. the analog routing architecture is di vided into four quadrants as shown in figure 8-2 . each quadrant has four analog globals (agl[0..3], agl[4..7], agr[0..3 ], agr[4..7]). each gpio is connected to the corresponding ag through an analog switch. the analog mux bus is a shared routing resource that connects to every gpio through an analog switch. there are two amuxbus routes in cy8c36, one in the left half (amuxbusl) and one in the right half (amuxbusr), as shown in figure 8-2 . analog interface precision reference sc/ct block cmp cmp cmp cmp capsense subsystem dsi array clock distribution decimator config & status registers phub cpu comparators gpio port gpio port dac dac delsig adc dac dac op amp op amp a n a l o g r o u t i n g a n a l o g r o u t i n g op amp op amp sc/ct block sc/ct block sc/ct block
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 55 of 131 figure 8-2. cy8c36 analog interconnect vddio0 sio p12[3] sio p12[2] gpio p15[3] gpio p15[2] sio p12[1] sio p12[0] gpio p3[7] gpio p3[6] vddio3 vccd vssd vddd gpio p6[0] gpio p6[3] gpio p6[2] gpio p6[1] gpio p15[4] gpio p15[5] gpio p2[0] gpio p2[4] gpio p2[3] gpio p2[2] gpio p2[1] vddio2 gpio p2[5] gpio p2[7] gpio p2[6] sio p12[4] sio p12[5] gpio p6[4] gpio p6[5] gpio p6[6] gpio p6[7] vddio1 sio p12[6] sio p12[7] usb io p15[6] usb io p15[7] vddd vssd vccd gpxt p15[0] gpxt p15[1] gpio p3[5] gpio p3[4] gpio p3[3] gpio p3[2] gpio p3[1] agr[4] agr[7] agr[6] agr[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] *** * * * * * * * * * denotes pins on all packages dsm v0 v2 v1 v3 i1 i3 i0 i2 vidac 76543210 76543210 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 comp0 comp2 comp1 comp3 comparator agl[4] agl[7] agl[6] agl[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] agr[4] agr[7] agr[6] agr[5] notes: amuxbusr amuxbusl i1 i3 i2 i0 rev #60 13-feb-2012 opamp0 vssa vssd vcca gpio p0[5] * gpio p0[7] * gpio p1[3] gpio p1[2] gpio p1[1] gpio p1[0] * * * * gpio p1[4] * gpio p1[5] * gpio p1[6] * gpio p1[7] * gpio p5[7] gpio p5[6] gpio p5[5] gpio p5[4] gpio p4[4] gpio p4[7] gpio p4[6] gpio p4[5] gpio p5[2] gpio p5[3] gpio p5[1] gpio p5[0] gpio p4[3] gpio p4[2] abusl0 * * ** * * * * * * * * * * * agl[4] agl[7] agl[6] agl[5] gpio p4[0] gpio p4[1] vssa amuxbusl amuxbusr amuxbusl amuxbusr amuxbusl amuxbusr abusl1 abusl2 abusl3 abusr3 abusr2 abusr1 abusr0 exvrefl exvrefr ind vssb vboost xres vssd * * * * vbat exvrefr exvrefl + - qtz_ref refs gpio p3[0] gpio p0[6] * lpf in0 out0 in1 out1 sc0 sc1 sc2 sc3 vin vref out out out sc/ct out mux group switch group connection large ( ~200 ohms) small ( ~870 ohms ) switch resistance vin vref vin vref vin vref vss ref ts adc gpio p0[0] * gpio p0[1] * gpio p0[2] * gpio p0[3] * gpio p0[4] * amuxbusr amuxbusl analog globals analog bus 0123 3210 analog bus analog globals refbufr refbufl in out ref in out ref vssa capsense vssa exvrefl1 opamp2 opamp3 opamp1 exvrefl2 cmp0_vref (1.024v) vref_cmp1 (0.256v) vdda sc0_bgref (1.024v) refbuf_vref1 (1.024v) refbuf_vref2 (1.2v) dac_vref (0.256v) dsm0_vcm_vref1 (0.8v) dsm0_qtz_vref2 (1.2v) abuf_vref_int (1.024v) 3210 0123 lcd signals are not shown. * : vdda * vbe vref_vss_ext sc2_bgref (1.024v) sc1_bgref (1.024v) sc3_bgref (1.024v) dsm0_vcm_vref2 (0.7v) vcmsel[1:0] vdda/3 vdda/4 refmux[2:0] dsm0_qtz_vref1 (1.024v) vcm dac0 dac2 dac1 dac3 dsm0 + - + - + - + - cmp_muxvn[1:0] vdda/2 bg_vda_swabusl0 cmp1_vref cmp1_vref cmp1_vref refsel[1:0] refbufl_ cmp refbufr_ cmp cmp0_vref (1.024v) abuf_vref_int (1.024v) bg_vda_res_en refbuf_vref1 (1.024v) refbuf_vref2 (1.2v) refsel[1:0] swout swin swout swin swfol swfol swfol swfol swinn swinn swinp swinp swinp swinn swinp swinn lpf vssd
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 56 of 131 analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. there are eight abus routes in cy8c36, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in figure 8-2 . using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. a multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. in figure 8-2 , multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. 8.2 delta-sigma adc the cy8c36 device contains one delta-sigma adc. this adc offers differential input, high resolution and excellent linearity, making it a good adc choice for measurement applications. the converter can be configured to output 12-bit resolution at data rates of up to 192 ksps. at a fi xed clock rate, resolution can be traded for faster data rates as shown in ta b l e 8 - 1 and figure 8-3 . figure 8-3. delta-sigma adc samp le rates, range = 1.024 v 8.2.1 functional description the adc connects and configures three basic components, input buffer, delta-sigma modulator, and decimator. the basic block diagram is shown in figure 8-4 . the signal from the input muxes is delivered to the delta-si gma modulator either directly or through the input buffer. the delt a-sigma modulator performs the actual analog to digital conversion. the modulator over-samples the input and generates a serial data stream output. this high speed data stream is not useful for most applications without some type of post processing, and so is passed to the decimator through the analog interface block. the decimator converts the high speed serial data stream into parallel adc results. the modulator/decimator frequency response is [(sin x)/x] 4 ; a typical frequency response is shown in figure 8-5 . figure 8-4. delta-sigma adc block diagram figure 8-5. delta-sigma adc frequency response, normalized to output, sample rate = 48 khz resolution and sample rate are controlled by the decimator. data is pipelined in the decimator; the output is a function of the last four samples. when the i nput multiplexer is switched, the output data is not valid until af ter the fourth sample after the switch. 8.2.2 operational modes the adc can be configured by the us er to operate in one of four modes: single sample, multi sample, continuous, or multi sample (turbo). all four modes are started by either a write to the start bit in a control register or an assertion of the start of conversion (soc) signal. when the conversion is complete, a status bit is set and the output signal end of conversion (eoc) asserts high and remains high until the value is read by either the dma controller or the cpu. 8.2.2.1 single sample in single sample mode, the adc performs one sample conversion on a trigger. in this mode, the adc stays in standby state waiting for the soc signal to be asserted. when soc is signaled the adc performs four successive conversions. the first three conversions prime the decimator. the adc result is table 8-1. delta-sigma adc performance bits maximum sample rate (sps) sinad (db) 12 192 k 66 8 384 k 43 100 1,000 10,000 100, 000 1,000,000 7 8 9 10111213 continuous multi-sample sample rates, sps resolution, bits delta sigma modulator decimator 12 to 20 bit result eoc soc positive input mux negative input mux (analog routing) input buffer frequency response. db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 1,000 10,000 100,000 1,000,000 input frequency, hz input frequency, hz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 57 of 131 valid and available after the fourth conversion, at which time the eoc signal is generated. to detect the end of conversion, the system may poll a control register for status or configure the external eoc signal to generate an interrupt or invoke a dma request. when the transfer is done the adc reenters the standby state where it stays until another soc event. 8.2.2.2 continuous continuous sample mode is us ed to take multiple successive samples of a single input signal. multiplexing multiple inputs should not be done with this mode. there is a latency of three conversion times before the first conversion result is available. this is the time required to prime the decimator. after the first result, successive conversions are available at the selected sample rate. 8.2.2.3 multi sample multi sample mode is similar to continuous mode except that the adc is reset between samples. this mode is useful when the input is switched between multiple signals. the decimator is re-primed between each sample so that previous samples do not affect the current conversion. upon completion of a sample, the next sample is auto matically initiated. the results can be transferred using either firmware polling, interrupt, or dma. more information on output formats is provided in the technical reference manual. 8.2.3 start of conversion input the soc signal is used to start an adc conversion. a digital clock or udb output can be used to drive this input. it can be used when the sampling period must be longer than the adc conversion time or when the adc must be synchronized to other hardware. this signal is optional and does not need to be connected if adc is running in a continuous mode. 8.2.4 end of conversion output the eoc signal goes high at the end of each adc conversion. this signal may be used to trigger either an interrupt or dma request. 8.3 comparators the cy8c36 family of devices contains four comparators in a device. comparators have these features: ? input offset factory trimmed to less than 5 mv ? rail-to-rail common mode input range (v ssa to v dda ) ? speed and power can be traded off by using one of three modes: fast, slow, or ultra low-power ? comparator outputs can be routed to lookup tables to perform simple logic functions and then can also be routed to digital blocks ? the positive input of the comp arators may be optionally passed through a low pass filter. two filters are provided ? comparator inputs can be connections to gpio, dac outputs and sc block outputs 8.3.1 input and output interface the positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. the output from each comparator could be routed to any of the two input luts. the output of that lut is routed to the udb digital system interface. figure 8-6. analog comparator anaif + _ + + _ comp2 _ comp0 comp1 + _ comp3 4 lut0 lut1 lut2 lut3 4 4 4 4 4 4 4 from analog routing from analog routing from analog routing from analog routing udbs
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 58 of 131 8.3.2 lut the cy8c36 family of devices contains four luts. the lut is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. the output of any lut is routed to the digital system interface of the udb array. from the digital system interface of the udb array, these signals can be connected to udbs, dma contro ller, i/o, or the interrupt controller. the lut control word written to a register sets the logic function on the output. the available lu t functions and the associated control word is shown in ta b l e 8 - 2 . 8.4 opamps the cy8c36 family of devices contain up to four general purpose opamps in a device. figure 8-7. opamp the opamp is uncommitted and can be configured as a gain stage or voltage follower, or output buffer on external or internal signals. see figure 8-8 . in any configuration, the input and output signals can all be connected to the internal global signals and monitored with an adc, or comparator. the configurations are implemented with switches between the signals and gpio pins. figure 8-8. opamp configurations the opamp has three speed modes, slow, medium, and fast. the slow mode consumes the least amount of quiescent power and the fast mode consumes the most power. the inputs are able to swing rail-to-rail. the output swing is capable of rail-to-rail operation at low current output, wit hin 50 mv of the rails. when driving high current loads (about 25 ma) the output voltage may only get within 500 mv of the rails. 8.5 programmable sc/ct blocks the cy8c36 family of devices contains up to four switched capacitor/continuous time (sc/ct) blocks in a device. each switched capacitor/continuous time block is built around a single rail-to-rail high bandwidth opamp. switched capacitor is a circuit design technique that uses capacitors plus switches instead of resistors to create analog functions. these circuits work by moving charge between capacitors by opening and closing different switches. nonoverlapping in phase clock si gnals control the switches, so that not all switches are on simultaneously. the psoc creator tool offers a user friendly interface, which allows you to easily program the sc/ct blocks. switch control and clock phase control configur ation is done by psoc creator so users only need to determine the application use parameters such as gain, amplifier polarity, v ref connection, and so on. table 8-2. lut function vs. program word and inputs control word output (a and b are lut inputs) 0000b false (?0?) 0001b a and b 0010b a and (not b ) 0011b a 0100b (not a ) and b 0101b b 0110b a xor b 0111b a or b 1000b a nor b 1001b a xnor b 1010b not b 1011b a or (not b ) 1100b not a 1101b (not a ) or b 1110b a nand b 1111b true (?1?) opamp vref gpio gpio = analog switch gpio analog global bus analog internal bus analog global bus opamp vout to pin vin vout to gpio vp to gpio b) external uncommitted opamp a) voltage follower vout to pin vp vn to internal signals c) internal uncommitted opamp vn to gpio gpio pin opamp opamp
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 59 of 131 the same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. the opamp and resistor array is programmable to perform various analog functions including ? naked operational amplifier ? continuous mode ? unity-gain buffer ? continuous mode ? programmable gain amplifier (pga) ? continuous mode ? transimpedance amplifier (tia) ? continuous mode ? up/down mixer ? continuous mode ? sample and hold mixer (nrz s/h) ? switched cap mode ? first order analog to digital modulator ? switched cap mode 8.5.1 naked opamp the naked opamp presents both inputs and the output for connection to internal or external signals. the opamp has a unity gain bandwidth greater than 6.0 mhz and output dr ive current up to 650 a. this is sufficient for buffering internal signals (such as dac outputs) and driving external loads greater than 7.5 k ? . 8.5.2 unity gain the unity gain buffer is a naked opamp with the output directly connected to the inverting input for a gain of 1.00. it has a ?3 db bandwidth greater than 6.0 mhz. 8.5.3 pga the pga amplifies an external or internal signal. the pga can be configured to operate in inverting mode or noninverting mode. the pga function may be configured for both positive and negative gains as high as 50 and 49 respectively. the gain is adjusted by changing the values of r1 and r2 as illustrated in figure 8-9 on page 59. the schematic in figure 8-9 on page 59 shows the configuration and possible resistor settings for the pga. the gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. the bandwidth for each gain case is listed in ta b l e 8 - 3 . figure 8-9. pga resistor settings the pga is used in applications where the input signal may not be large enough to achieve the desired resolution in the adc, or dynamic range of another sc/ct block such as a mixer. the gain is adjustable at runtime, incl uding changing the gain of the pga prior to each adc sample. 8.5.4 tia the transimpedance amplifier (tia ) converts an internal or external current to an output vo ltage. the tia uses an internal feedback resistor in a continuous time configuration to convert input current to output voltage. for an input current i in , the output voltage is v ref - i in x r fb , where v ref is the value placed on the non inverting input. the feedback resistor rfb is programmable between 20 k ? and 1 m ? through a configuration register. ta b l e 8 - 4 shows the possible values of rfb and associated configuration settings. figure 8-10. continuous time tia schematic the tia configuration is used for applications where an external sensor's output is current as a fu nction of some type of stimulus such as temperature, light, magnetic flux etc. in a common application, the voltage dac output can be connected to the v ref tia input to allow calibration of the external sensor bias current by adjusting the voltage dac output voltage. 8.6 lcd direct drive the psoc liquid crystal display (lcd) driver system is a highly configurable peripheral designed to allow psoc to directly drive a broad range of lcd glass. all voltages are generated on chip, eliminating the need for extern al components. with a high multiplex ratio of up to 1/16, the cy8c36 family lcd driver system can drive a maximum of 736 segments. the psoc lcd driver module was also designed with the conservative power budget of portable devices in mind, enabling different lcd drive modes and power down modes to conserve power. table 8-3. bandwidth gain bandwidth 1 6.0 mhz 24 340 khz 48 220 khz 50 215 khz r1 r2 20 k to 980 k s 20 k or 40 k 1 0 1 0 v in v ref v ref v in table 8-4. feedback resistor settings configuration word nominal r fb ( k ? ) 000b 20 001b 30 010b 40 011b 60 100b 120 101b 250 110b 500 111b 1000 v ref v out i in r fb
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 60 of 131 psoc creator provides an lcd segment drive component. the component wizard provides easy and flexible configuration of lcd resources. you can specify pins for segments and commons along with other options. the software configures the device to meet the required specifications. this is possible because of the programmabilit y inherent to psoc devices. key features of the psoc lcd segment system are: ? lcd panel direct driving ? type a (standard) and type b (low-power) waveform support ? wide operating voltage range support (2 v to 5 v) for lcd panels ? static, 1/2, 1/3, 1/4, 1/5 bias voltage levels ? internal bias voltage generation through internal resistor ladder ? up to 62 total common and segment outputs ? up to 1/16 multiplex for a maximum of 16 backplane/common outputs ? up to 62 front plane/segment outputs for direct drive ? drives up to 736 total segments (16 backplane 46 front plane) ? up to 64 levels of software controlled contrast ? ability to move display data from memory buffer to lcd driver through dma (without cpu intervention) ? adjustable lcd refresh rate from 10 hz to 150 hz ? ability to invert lcd display for negative image ? three lcd driver drive modes, allowing power optimization figure 8-11. lcd system 8.6.1 lcd segment pin driver each gpio pin contains an lcd driver circuit. the lcd driver buffers the appropriate output of the lcd dac to directly drive the glass of the lcd. a register setting determines whether the pin is a common or segment. the pin?s lcd driver then selects one of the six bias voltages to drive the i/o pin, as appropriate for the display data. 8.6.2 display data flow the lcd segment driver syst em reads display data and generates the proper output voltages to the lcd glass to produce the desired image. display data resides in a memory buffer in the system sram. each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer in to the port data registers through dma. 8.6.3 udb and lcd segment control a udb is configured to generate the global lcd control signals and clocking. this set of signals is routed to each lcd pin driver through a set of dedicated lcd global routing channels. in addition to generating the global lcd control signals, the udb also produces a dma request to initiate the transfer of the next frame of lcd data. 8.6.4 lcd dac the lcd dac generates the cont rast control and bias voltage for the lcd system. the lcd dac produces up to five lcd drive voltages plus ground, based on the selected bias ratio. the bias voltages are driven out to gpio pins on a dedicated lcd bias bus, as required. 8.7 capsense the capsense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity det ection, etc. the capsense system uses a configuration of system resources, including a few hardware functions primarily targeted for capsense. specific resource usage is detailed in the capsense component in psoc creator. a capacitive sensing method using a delta-sigma modulator (csd) is used. it provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. 8.8 temp sensor die temperature is used to establish programming parameters for writing flash. die temperatur e is measured using a dedicated sensor based on a forward biased transistor. the temperature sensor has its own auxiliary adc. 8.9 dac the cy8c36 parts contain up to four digital to analog convertors (dacs). each dac is 8-bit and can be configured for either voltage or current output. the dacs support capsense, power supply regulation, and waveform generation. each dac has the following features: ? adjustable voltage or current output in 255 steps ? programmable step size (range selection) ? eight bits of calibration to correct 25% of gain error ? source and sink option for current output ? high and low speed / power modes ? 8 msps conversion rate for current output ? 1 msps conversion rate for voltage output ? monotonic in nature ? data and strobe inputs can be provided by the cpu or dma, or routed directly from the dsi lcd driver block udb dma display ram lcd dac pin global clock phub
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 61 of 131 ? dedicated low-resistance output pin for high-current mode figure 8-12. dac block diagram 8.9.1 current dac the current dac (idac) can be configured for the ranges 0 to 31.875 a, 0 to 255 a, and 0 to 2.04 ma. the idac can be configured to source or sink current. 8.9.2 voltage dac for the voltage dac (vdac), t he current dac output is routed through resistors. the two ranges available for the vdac are 0 to 1.02 v and 0 to 4.08 v. in voltage mode any load connected to the output of a dac should be pu rely capacitive (the output of the vdac is not buffered). 8.10 up/down mixer in continuous time mode, the sc/ct block components are used to build an up or down mixer. any mixing application contains an input signal frequency and a local oscillator frequency. the polarity of the clock, fclk, switches the amplifier between inverting or noninverting gain. th e output is the product of the input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the signal frequency (fclk + fin and fclk ? fin) and reduced-level frequency components at odd integer multiples of the local oscillator frequency. the local oscillator frequency is provided by the selected clock source for the mixer. continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 mhz. figure 8-13. mixer configuration 8.11 sample and hold the main application for a sample and hold, is to hold a value stable while an adc is performing a conversion. some applications require multiple signals to be sampled simultaneously, such as for power calculations (v and i). reference ? source ? scaler ? i source ? range ? 1x , ? 8x , ? 64x i sink ? range ???? 1x , ? 8x , ? 64x ? r ? ? 3r ? ? vout ? ? iout ? ? r mix 0 20 k or 40 k r mix 0 20 k or 40 k sc_clk sc_clk vin c2 = 1.7 pf c1 = 850 ff
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 62 of 131 figure 8-14. sample and hold topology ( ? 1 and ? 2 are opposite phases of a clock) 8.11.1 down mixer the sc/ct block can be used as a mixer to down convert an input signal. this circuit is a high bandwidth passive sample network that can sample input signals up to 14 mhz. this sampled value is then held using the opamp with a maximum clock rate of 4 mhz. the output frequency is at the difference between the input frequency and the highest integer multiple of the local oscillator that is less than the input. 8.11.2 first order modulator ? sc mode a first order modulator is constructed by placing the sc/ct block in an integrator mode and using a comparator to provide a 1-bit feedback to the input. depending on this bit, a reference voltage is either subtracted or added to the input signal. the block output is the output of the comparator and not the integrator in the modulator case. the signal is downshifted and buffered and then processed by a decimator to make a delta-sigma converter or a counter to make an incremental converter. the accuracy of the sampled data from the first-order modulator is determined from several factors. the main application for this modulator is for a low frequency adc with high accuracy. applications include strain gauges, thermocouples, precision voltage, and current measurement. 9. programming, debug interfaces, resources psoc devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. three interfaces are available: jtag, swd, and swv. jtag and swd support all programming and debug features of the device. jtag also supports standard jtag scan chains for board level test and chaining multiple jtag devices to a single jtag connection. for more information on psoc 3 programming, refer to the application note an62391 - in-system programming for psoc ? 3. complete debug on chip (doc) functionality enables full device debugging in the final system using the stan dard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator ide software provides fully integrated programming and debug support for psoc devices. the low cost miniprog3 programmer and debugger is designed to provide full programming and debug support of psoc devices in conjunction with the psoc creator ide. psoc jtag, swd, and swv interfaces are compatible with industry standard third party tools. all doc circuits are disabled by default and can only be enabled in firmware. if not enabled, the only way to reenable them is to erase the entire device, clear fl ash protection, and reprogram the device with new firmware that enables doc. disabling doc features, robust flash protection, and hiding custom analog and digital functionality inside the psoc device provide a level of security not possible with multichip application solutions. additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously re programmed device. permanently disabling interfaces is not recommended in most applications because the you cannot access the device later. because all programming, debug, and test interfaces are disabled when device security is enabled, psocs with device security enabled may not be returned for failure analysis. 9.1 jtag interface the ieee 1149.1 compliant jtag interface exists on four or five pins (the ntrst pin is optional). the jtag interface is used for programming the flash memory, debugging, i/o scan chains, and jtag device chaining. psoc 3 has certain timing requirements to be met for entering programming mode through the jtag interface. due to these timing requirements, not all standard jtag programmers, or standard jtag file formats such as svf or stapl, can support psoc 3 programming. the list of programmers that support psoc 3 programming is available at http://www.cypress.co m/go/programming . the jtag clock frequency can be up to 14 mhz, or 1/3 of the cpu clock frequency for 8 and 16-bit transfers, or 1/5 of the cpu clock frequency for 32-bit transfers. by default, the jtag pins are enabled on new devices but the jt ag interface can be disabled, allowing these pins to be used as gpio instead. v i n v ref v out 1 2 c 1 c 2 2 1 1 2 1 2 1 1 2 2 c 3 c 4 v ref v ref ? ? ? ? ? ? ? ? ? ? ? ? table 9-1. debug configurations debug and trace configuration gpio pins used all debug and trace disabled 0 jtag 4 or 5 swd 2 swv 1 swd + swv 3
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 63 of 131 figure 9-1. jtag interface connections between psoc 3 and programmer tck ? (p1[1] tms ? (p1[0]) ?? 5 gnd gnd tck tms ?? 5 xres host programmer psoc 3 tdo tdi (p1[4]) tdi tdo (p1[3]) ntrst ? 6 ntrst (p1[5]) 6 1 the voltage levels of host programmer and the psoc 3 voltage domains involved in programming should be same. the port 1 jtag pins, xres pin (xres_n or p1[2]) are powered by v ddio1 . so, v ddio1 of psoc 3 should be at same voltage level as host v dd . rest of psoc 3 voltage domains ( ? v ddd , ? v dda , ? v ddio0 , ? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. 2 vdda must be greater than or equal to all other power supplies (vddd, vddio?s) in psoc 3. 3 for power cycle mode programming, xres pin is no t required. but the host programmer must have the capability to toggle power (vddd, vdda, all vddio?s) to psoc 3. this may typically require external interface circuitry to toggle power which will depend on the programming setup. the power supplies can be brought up in any sequence, however, once stable, vdda must be greater than or equal to all other supplies. 4 for jtag programming, device reset c an also be done without co nnecting to the xres pin or power cycle mode by using the tms,tck,tdi, tdo pins of psoc 3, and writing to a specific register. but this requires that the dps setting in nvl is not equal to ?debug ports disabled?. 5 by default, psoc 3 is configured for 4-wire jtag mode unless user changes the dps setting. so the tms pin is unidirectional. but if the dps setting is changed to non-jtag mode, the tms pin in jtag is bi-directional as the swd protocol has to be used for acquiring the psoc 3 device initially. after switching from swd to jtag mode, the tms pin will be uni-directional. in such a case, unidirectional buffer should not be used on tms line. 6 ntrst jtag pin (p1[5]) cannot be used to reset the jtag tap controlller during first time programming of psoc 3 as the default setting is 4-wire jtag (ntrst disabled). use the tms, tck pins to do a reset of jtag tap controller. 7 if xres pin is used by host, p1[2] will be configured as xres by default only for 48-pin devices (without dedicated xres pin). for devices with dedicated xres pin, p1[2] is gpio pin by default. so use p1[2] as reset pin only for 48-pin devices, but use dedicate d xres pin for rest of devices. v ddd , ? v dda , ? v ddio0 , ? v ddio1 , ? v ddio2 , ? v ddio3 1, 2, 3, 4 v ssd , ? v ssa xres ? or ? p1[2] ? 4, ? 7 v dd v dd
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 64 of 131 9.2 serial wire debug interface the swd interface is the prefe rred alternative to the jtag interface. it requires only two pins instead of the four or five needed by jtag. swd provides all of the programming and debugging features of jtag at the same speed. swd does not provide access to scan chains or device chaining. the swd clock frequency can be up to 1/3 of the cpu clock frequency. swd uses two pins, either two of the jtag pins (tms and tck) or the usbio d+ and d? pins. the usbio pins are useful for in system programming of usb so lutions that would otherwise require a separate programming connector. one pin is used for the data clock and the other is used for data input and output. swd can be enabled on only one of the pin pairs at a time. this only happens if, within 8 s (key window) after reset, that pin pair (jtag or usb) receives a predetermined sequence of 1s and 0s. swd is used for debugging or for programming the flash memory. the swd interface can be enabled from the jtag interface or disabled, allowing its pins to be used as gpio. unlike jtag, the swd interface can always be reacquired on any device during the key window. it can then be used to reenable the jtag interface, if desired. when using swd or jtag pins as standard gpio, make sure that the gpio functionality and pcb circuits do not interfere with swd or jtag use. figure 9-2. swd interface connections between psoc 3 and programmer v ssd , ? v ssa v ddd , ? v dda , ? v ddio0 , ? v ddio1 , ? v ddio2 , ? v ddio3 1, 2, 3 swdck ? (p1[1] ? or ? p15[7]) swdio ? (p1[0] ? or ? p15[6]) xres ? or ? p1[2] ?? 3, ? 4 gnd gnd swdck swdio xres host programmer psoc 3 v dd 1 the voltage levels of the host programmer and the psoc 3 voltage domains involved in programming should be the same. xres pin (xres_n or p1[2]) is powered by v ddio1 . the usb swd pins are powered by v ddd . so for programming using the usb swd pins with xres pin, the v ddd , v ddio1 ? of psoc 3 should be at the same voltage level as host v dd . rest of psoc 3 voltage domains ( ? v dda , ? v ddio0 , ?? ???? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. the port 1 swd pins are powered by v ddio1 . so v ddio1 of psoc 3 should be at same voltage level as host v dd for port 1 swd programming. rest of psoc 3 voltage domains ( ? v ddd , ?? v dda , ? v ddio0 , ? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. 2 vdda must be greater than or equal to all other power supplies (vddd, vddio?s) in psoc 3. 3 for power cycle mode programming, xres pin is not required. but the host programmer must have the capability to toggle power (vddd, vdda, all vddio?s) to psoc 3. this may typically require external interface circuitry to toggle power which will depend on the programming setup. the power supplies can be brought up in any sequence, however, once stable, vdda must be greater than or equal to all other supplies. 4 p1[2] will be configured as xres by default only for 48-pin devices (without dedicated xres pin). for devices with dedicated xres pin, p1[2] is gpio pin by default. so use p1[2] as reset pin only for 48- pin devices, but use dedicated xres pin for rest of devices. v dd
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 65 of 131 9.3 debug features using the jtag or swd interface, the cy8c36 supports the following debug features: ? halt and single-step the cpu ? view and change cpu and peri pheral registers, and ram addresses ? eight program address breakpoints ? one memory access breakpoint?break on reading or writing any memory address and data value ? break on a sequence of breakpoints (non recursive) ? debugging at the full speed of the cpu ? compatible with psoc creator and miniprog3 programmer and debugger ? standard jtag programming and debugging interfaces make cy8c36 compatible with other popular third-party tools (for example, arm / keil) 9.4 trace features the cy8c36 supports the following trace features when using jtag or swd: ? trace the 8051 program counter (pc), accumulator register (acc), and one sfr / 8051 core ram register ? trace depth up to 1000 instructions if all registers are traced, or 2000 instructions if only th e pc is traced (on devices that include trace memory) ? program address trigger to start tracing ? trace windowing, that is, only trace when the pc is within a given range ? two modes for handling trace buffer full: continuous (overwriting the oldest trace data) or break when trace buffer is full 9.5 single wire viewer interface the swv interface is closely associated with swd but can also be used independently. swv data is output on the jtag interface?s tdo pin. if using sw v, you must configure the device for swd, not jtag. swv is not supported with the jtag interface. swv is ideal for application debug where it is helpful for the firmware to output data similar to 'printf' debugging on pcs. the swv is ideal for data monitoring, because it requires only a single pin and can output data in standard uart format or manchester encoded format. for example, it can be used to tune a pid control loop in which the output and graphing of the three error terms greatly simplifies coefficient tuning. the following features are supported in swv: ? 32 virtual channels, each 32 bits long ? simple, efficient packing and serializing protocol ? supports standard uart format (n81) 9.6 programming features the jtag and swd interfaces provide full programming support. the entire device can be erased, programmed, and verified. you can increase flash protection levels to protect firmware ip. flash protection can only be reset after a full device erase. individual flash blocks can be erased, programmed, and verified, if block security settings permit. 9.7 device security psoc 3 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. the device security is activate d by programming a 32-bit key (050536f43) to a write once latch (wol). the wol is a type of nonvolatile latch (nvl). the cell itself is an nvl with additional logic wrapped around it. each wol device contains four bytes (32 bits) of data. the wrapper outputs a ?1? if a super-majority (28 of 32) of its bits match a pre-determined pattern (050536f43); it outputs a ?0? if this majority is not reached. when the outpu t is 1, the write once nv latch locks the part out of debug and test modes; it also permanently gates off the ability to erase or alter the contents of the latch. matching all bits is intentionally not required, so that single (or few) bit failures do not deassert the wol output. t he state of the nvl bits after wafer processing is truly random with no tendency toward 1 or 0. the wol only locks the part af ter the correct 32-bit key (050536f43) is loaded into the nvl's volatile memory, programmed into the nvl's nonvolat ile cells, and the part is reset. the output of the wol is only sampled on reset and used to disable the access. this pr ecaution prevents anyone from reading, erasing, or altering the contents of the internal memory. the user can write the key into the wol to lock out external access only if no flash protection is set (see ?flash security? on page 21). however, after setting the values in the wol, a user still has access to the part until it is rese t. therefore, a user can write the key into the wol, pr ogram the flash protection data, and then reset the part to lock it. if the device is protected with a wol setting, cypress cannot perform failure analysis and, th erefore, cannot accept rmas from customers. the wol can be read out through the swd port to electrically identify protected parts. the user can write the key in wol to lock out external access only if no flash protection is set. for more information on how to take full advantage of the security features in psoc see the psoc 3 trm. disclaimer note the following details of the fl ash code protection features on cypress devices. cypress products meet the specifications contained in their particular cypress data sheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. an y of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? cypress is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress are committed to continuously improving the code protecti on features of our products.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 66 of 131 10. development support the cy8c36 family has a rich set of documentation, development tools, and online resources to assist you during your development process. visit psoc.cypress.com/ getting-started to find out more. 10.1 documentation a suite of documentation, suppor ts the cy8c36 family to ensure that you can find answers to your questions quickly. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in detail, how to use source control with psoc creator, and much more. component data sheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component data sheets provide all of the information needed to select and use a particular component, including a functional description, api documentation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include brushless dc motor control and on-chip filtering. application notes often include example projects in addition to the application note document. technical reference manual : the technical reference manual (trm) contains all the technical detail you need to use a psoc device, including a co mplete description of all psoc registers. 10.2 online in addition to print documentation, the cypress psoc forums connect you with fellow psoc user s and experts in psoc from around the world, 24 hours a day, 7 days a week. 10.3 tools with industry standard cores, programming, and debugging interfaces, the cy8c36 family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use psoc creator ide, supported third party compilers, programmers, debuggers, and development kits.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 67 of 131 11. electrical specifications specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. the unique flexibility of the psoc udbs and analog blocks enable many functions to be implemented in psoc creator components, see the component data sheets for full ac/dc specifications of individual functions. see the ?example peripherals? section on page 41 for further expl anation of psoc creator components. 11.1 absolute maximum ratings note usage above the absolute maximum conditions listed in ta b l e 11 - 1 may cause permanent damage to the device. exposure to maximum conditions for extended periods of time may affect de vice reliability. when used below maximum conditions but above normal operating conditions the device may not operate to specification. table 11-1. absolute maximum ratings dc specifications parameter description conditions min typ max units t stg storage temperature higher storage temperatures reduce nvl data retention time. recommended storage temper- ature is +25 c 25 c. extended duration storage temperatures above 85 c degrade reliability. ?55 25 100 c v dda analog supply voltage relative to v ssa ?0.5 ? 6 v v ddd digital supply voltage relative to v ssd ?0.5 ? 6 v v ddio i/o supply voltage relative to v ssd ?0.5 ? 6 v v cca direct analog core voltage input ?0.5 ? 1.95 v v ccd direct digital core voltage input ?0.5 ? 1.95 v v ssa analog ground voltage v ssd ? 0.5 ? v ssd + 0.5 v v gpio [21] dc input voltage on gpio includes signals sourced by v dda and routed internal to the pin v ssd ? 0.5 ? v ddio + 0.5 v v sio dc input voltage on sio output disabled v ssd ? 0.5 ? 7 v output enabled v ssd ? 0.5 ? 6 v v ind voltage at boost converter input 0.5 ? 5.5 v v bat boost converter supply v ssd ? 0.5 ? 5.5 v i vddio current per v ddio supply pin ? ? 100 ma i gpio gpio current ?30 ? 41 ma i sio sio current ?49 ? 28 ma i usbio usbio current ?56 ? 59 ma v extref adc external reference in puts pins p0[3], p3[2] ? ? 2 v lu latch up current [22] ?140 ? 140 ma esd hbm electrostatic discharge voltage, human body model v ssa tied to v ssd 2200 ? ? v v ssa not tied to v ssd 750 ? ? v esd cdm electrostatic discharge voltage, charge device model 500 ? ? v notes 21. the v ddio supply voltage must be greater than the maximum voltage on the associated gpio pins. maximum voltage on gpio pin ?? v ddio ? v dda . 22. meets or exceeds jedec spec eia/jesd78 ic latch-up test.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 68 of 131 11.2 device level specifications specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.2.1 device level specifications table 11-2. dc specifications parameter description conditions min typ [25] max units i dd [23][24] active mode only imo and cpu clock enabled. cpu executing simple loop from instruction buffer. v ddx = 2.7 v ? 5.5 v; f cpu = 6 mhz t = ?40 c ? 1.2 2.9 ma t = 25 c ? 1.2 3.1 t = 85 c ? 4.9 7.7 imo enabled, bus clock and cpu clock enabled. cpu executing complex program from flash. v ddx = 2.7 v ? 5.5 v; f cpu = 3 mhz t = ?40 c ? 1.3 2.9 t = 25 c ? 1.6 3.2 t = 85 c ? 4.8 7.5 v ddx = 2.7 v ? 5.5 v; f cpu = 6 mhz t = ?40 c ? 2.1 3.7 t = 25 c ? 2.3 3.9 t = 85 c ? 5.6 8.5 v ddx = 2.7 v ? 5.5 v; f cpu = 12 mhz t = ?40 c ? 3.5 5.2 t = 25 c ? 3.8 5.5 t = 85 c ? 7.1 9.8 v ddx = 2.7 v ? 5.5 v; f cpu = 24 mhz t = ?40 c ? 6.3 8.1 t = 25 c ? 6.6 8.3 t = 85 c ? 10 13 v ddx = 2.7 v ? 5.5 v; f cpu = 48 mhz t = ?40 c ? 11.5 13.5 t = 25 c ? 12 14 t = 85 c ? 15.5 18.5 v ddx = 2.7 v ? 5.5 v; f cpu = 62 mhz t = ?40 c ? 16 18 t = 25 c ? 16 18 t = 85 c ? 19.5 23 notes 23. total current for all power domains: digital (i ddd ), analog (i dda ), and i/os (i ddio0 , 1, 2, 3). boost not included. all i/os floating. 24. the current consumption of additional per ipherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in psoc creator, the integrated design environment. to estimate to tal current, find the cpu current at the frequency of interest a nd add peripheral currents for your particular system from the device datasheet and component datasheets. 25. v ddx = 3.3 v.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 69 of 131 sleep mode [26] cpu = off rtc = on (= eco32k on, in low-power mode) sleep timer = on (= ilo on at 1 khz) [27] wdt = off i2c wake = off comparator = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 4.5 v - 5.5 v t = ?40 c ? 1.1 2.3 a t = 25 c ? 1.1 2.2 t = 85 c ? 15 30 v dd = v ddio = 2.7 v ? 3.6 v t = ?40 c ? 1 2.2 t = 25 c ? 1 2.1 t = 85 c ? 12 28 v dd = v ddio = 1.71 v ? 1.95 v [28] t = 25 c ? 2.2 4.2 comparator = on cpu = off rtc = off sleep timer = off wdt = off i2c wake = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 2.7 v ? 3.6 v t = 25 c ? 2.2 2.7 i2c wake = on cpu = off rtc = off sleep timer = off wdt = off comparator = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 2.7 v ? 3.6 v t = 25 c ? 2.2 2.8 hibernate mode [26] hibernate mode current all regulators and oscillators off sram retention gpio interrupts are active boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 4.5 v - 5.5 v t = ?40 c ? 0.2 0.6 a t = 25 c ? 0.5 0.6 t = 85 c ? 4.1 5.3 v dd = v ddio = 2.7 v ? 3.6 v t = ?40 c ? 0.2 0.6 t = 25 c ? 0.2 0.4 t = 85 c ? 3.2 4.2 v dd = v ddio = 1.71 v ? 1.95 v [28] t = ?40 c ? 0.2 0.6 t = 25 c ? 0.3 0.4 t = 85 c ? 3.3 4.3 table 11-2. dc specifications (continued) parameter description conditions min typ [25] max units notes 26. if v ccd and v cca are externally regulated, t he voltage difference between v ccd and v cca must be less than 50 mv. 27. sleep timer generates periodic interrupts to wake up the cpu. this specification applies only to those times that the cpu is off. 28. externally regulated mode.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 70 of 131 figure 11-1. active mode current vs f cpu , v dd = 3.3 v, temperature = 25 c figure 11-2. active mode current vs temperature and f cpu , v dd = 3.3 v figure 11-3. active mode current vs v dd and temperature, f cpu = 24 mhz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 71 of 131 figure 11-4. f cpu vs. v dd table 11-3. ac specifications [29] parameter description conditions min typ max units f cpu cpu frequency 1.71 v ? v ddd ? 5.5 v dc ? 67.01 mhz f busclk bus frequency 1.71 v ? v ddd ? 5.5 v dc ? 67.01 mhz svdd v dd ramp rate ? ? 0.066 v/s t io_init time from v ddd /v dda /v ccd /v cca ?? ipor to i/o ports set to their reset states ??10s t startup time from v ddd /v dda /v ccd /v cca ? pres to cpu executing code at reset vector v cca /v dda = regulated from v dda /v ddd , no pll used, fast imo boot mode (48 mhz typ.) ??33s v cca /v ccd = regulated from v dda /v ddd , no pll used, slow imo boot mode (12 mhz typ.) ??66s t sleep wakeup from sleep mode ? application of non?lvd interrupt to beginning of execution of next cpu instruction ??15s t hibernate wakeup from hibernate mode ? application of external interrupt to beginning of execution of next cpu instruction ? ? 100 s note 29. based on device characterization (not production tested). 5.5 v 1.71 v 0.5 v 0 v dc 1 mhz 10 mhz 67 mhz 3.3 v valid operating region valid operating region with smp cpu frequency vdd voltage
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 72 of 131 11.3 power regulators specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.3.1 digital core regulator figure 11-5. regulators v cc vs v dd figure 11-6. digital regulator psrr vs frequency and v dd 11.3.2 analog core regulator figure 11-7. analog regulator psrr vs frequency and v dd table 11-4. digital core regulator dc specifications parameter description conditions min typ max units v ddd input voltage 1.8 ? 5.5 v v ccd output voltage ? 1.80 ? v regulator output capacitor 10%, 5r ceramic or better. the two v ccd pins must be shorted together, with as short a trace as possible, see power system on page 29 ?1?f table 11-5. analog core regulator dc specifications parameter description conditions min typ max units v dda input voltage 1.8 ? 5.5 v v cca output voltage ? 1.80 ? v regulator output capacitor 10%, 5r ceramic or better ? 1 ? f
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 73 of 131 11.3.3 inductive boost regulator. table 11-6. inductive boost regulator dc specifications unless otherwise specified, ope rating conditions are: v bat = 2.4 v, v out = 2.7 v, i out = 40 ma, f sw = 400 khz, l boost = 10 h, c boost = 22 f || 0.1 f parameter description conditions min typ max units v bat input voltage includes startup t=-35 c to +65 c 0.5 ? 3.6 v over entire temperature range 0.68 ? 3.6 v i out load current, steady state [30, 31] v bat = 1.6 ? 3.6 v, v out = 3.6 ? 5.0 v, external diode ??50ma v bat = 1.6 ? 3.6 v, v out = 1.6 ? 3.6 v, internal diode ??75ma v bat = 0.8 ? 1.6 v, v out = 1.6 ? 3.6 v, internal diode ??30ma v bat = 0.8 ? 1.6 v, v out = 3.6 ? 5.0 v, external diode ??20ma v bat = 0.5 ? 0.8 v, v out = 1.6 ? 3.6 v, internal diode ??15ma i lpk inductor peak current ? ? 700 ma i q quiescent current boost active mode ? 200 ? a boost standby mode, 32 khz external crystal oscillator, i out < 1 a ?12 ? a v out boost voltage range [34, 33] 1.8 v 1.71 1.80 1.89 v 1.9 v 1.81 1.90 2.00 v 2.0 v 1.90 2.00 2.10 v 2.4 v 2.28 2.40 2.52 v 2.7 v 2.57 2.70 2.84 v 3.0 v 2.85 3.00 3.15 v 3.3 v 3.14 3.30 3.47 v 3.6 v 3.42 3.60 3.78 v 5.0 v external diode required 4.75 5.00 5.25 v reg load load regulation ? ? 3.8 % reg line line regulation ? ? 4.1 % notes 30. for output voltages above 3.6 v, an external diode is required. 31. maximum output current applies for output voltages ? 4x input voltage. 32. based on device characteri zation (not production tested). 33. at boost frequency of 400 khz, v out is limited to 4 x v bat . table 11-7. inductive boost regulator ac specifications unless otherwise specified, ope rating conditions are: v bat = 2.4 v, v out = 2.7 v, i out = 40 ma, f sw = 400 khz, l boost = 10 h, c boost = 22 f || 0.1 f. parameter description conditions min typ max units v ripple ripple voltage (peak-to-peak) 0.5 v < v bat < 1.7v, v out = 1.8 v, f sw = 400 khz, i out = 10 ma ? ? 100 mv
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 74 of 131 figure 11-8. efficiency vs v out i out = 5 ma, v bat = 0.6v, 1.2v, and 2.4v figure 11-9. efficiency vs v out i out = 30 ma, v bat = 0.6 v and 1.2 v figure 11-10. efficiency vs v out i out = 75 ma, v bat = 1.2 v figure 11-11. efficiency vs i out v bat = 2.4 v, v out = 3.3 v note 34. based on device characterization (not production tested). table 11-8. recommended external components for boost circuit parameter description conditions min typ max units l boost boost inductor ? 10 ? h c boost filter capacitor [34] 10 22 47 f i f external schottky diode average forward current external schottky diode is required for v out > 3.6 v 1? ? a v r 20 ? ? v
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 75 of 131 11.4 inputs and outputs specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. unless otherwise specified, all charts and graphs show typical values. when the power supplies ramp up, there are low-im pedance connections between each gpio pin and its v ddio supply. this causes the pin voltages to track v ddio until both v ddio and v dda reach the ipor voltage, which can be as high as 1.45 v. at that point, the low-impedance connections no longer exist and th e pins change to their normal nvl settings. 11.4.1 gpio notes 35. based on device characterization (not production tested). 36. for information on designing with psoc 3 oscillators, refer to the application note, an54439 - psoc ? 3 and psoc 5 external oscillator . table 11-9. gpio dc specifications parameter description conditions min typ max units v ih input voltage high threshold cmo s input, prt[]ctl = 0 0.7 ? v ddio ??v v il input voltage low threshold cmos input, prt[]ctl = 0 ? ? 0.3 ?? v ddio v v ih input voltage high threshold lvttl input, prt[]ctl = 1,v ddio < 2.7 v 0.7 v ddio ??v v ih input voltage high threshold lvttl input, prt[]ctl = 1, v ddio ? 2.7v 2.0 ? ? v v il input voltage low threshold lvttl input, prt[]ctl = 1,v ddio < 2.7 v ? ? 0.3 v ddio v v il input voltage low threshold lvttl input, prt[]ctl = 1, v ddio ? 2.7v ??0.8v v oh output voltage high i oh = 4 ma at 3.3 v ddio v ddio ? 0.6 ? ? v i oh = 1 ma at 1.8 v ddio v ddio ? 0.5 ? ? v v ol output voltage low i ol = 8 ma at 3.3 v ddio ??0.6v i ol = 4 ma at 1.8 v ddio ??0.6v rpullup pull-up resistor 3.5 5.6 8.5 k ? rpulldown pull-down resistor 3.5 5.6 8.5 k ? i il input leakage current (absolute value) [35] 25 c, v ddio = 3.0 v ? ? 2 na c in input capacitance [35] gpios not shared with opamp outputs, mhz eco or khzeco ?47pf gpios shared with mhz eco or khzeco [36] ?57pf gpios shared with opamp outputs ? ? 18 pf v h input voltage hysteresis (schmitt-trigger) [35] ?40?mv idiode current through protection diode to v ddio and v ssio ??100a rglobal resistance pin to analog global bus 25 c, v ddio = 3.0 v ? 320 ? ? rmux resistance pin to analog mux bus 25 c, v ddio = 3.0 v ? 220 ? ?
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 76 of 131 figure 11-12. gpio output high voltage and current figure 11-13. gpio output low voltage and current figure 11-14. gpio output rise and fall times, fast strong mode, v ddio = 3.3 v, 25 pf load figure 11-15. gpio output rise and fall times, slow strong mode, v ddio = 3.3 v, 25 pf load table 11-10. gpio ac specifications parameter description conditions min typ max units trisef rise time in fast strong mode [37] 3.3 v v ddio cload = 25 pf ? ? 12 ns tfallf fall time in fast strong mode [37] 3.3 v v ddio cload = 25 pf ? ? 12 ns trises rise time in slow strong mode [37] 3.3 v v ddio cload = 25 pf ? ? 60 ns tfalls fall time in slow strong mode [37] 3.3 v v ddio cload = 25 pf ? ? 60 ns fgpioout gpio output operating frequency ? ? ? ? 2.7 v < v ddio < 5.5 v, fast strong drive mode 90/10% v ddio into 25 pf ? ? 33 mhz 1.71 v < v ddio < 2.7 v, fast strong drive mode 90/10% v ddio into 25 pf ? ? 20 mhz 3.3 v < v ddio < 5.5 v, slow strong drive mode 90/10% v ddio into 25 pf ? ? 7 mhz 1.71 v < v ddio < 3.3 v, slow strong drive mode 90/10% v ddio into 25 pf ? ? 3.5 mhz fgpioin gpio input operating frequency 1.71 v < v ddio < 5.5 v 90/10% v ddio ??66mhz note 37. based on device characterizati on (not production tested).
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 77 of 131 11.4.2 sio notes 38. see figure 6-9 on page 36 and figure 6-12 on page 40 for more information on sio reference. 39. based on device characteriza tion (not production tested) table 11-11. sio dc specifications parameter description conditions min typ max units vinmax maximum input voltage all allowed values of v ddio and vddd, see section 11.2.1 ??5.5v vinref input voltage reference (differ- ential input mode) 0.5 ? 0.52 ?? v ddio v voutref output voltage reference (regulated output mode) v ddio > 3.7 1 ? v ddio ? 1 v v ddio < 3.7 1 ? v ddio ? 0.5 v v ih input voltage high threshold gpio mode cmos input 0.7 ? v ddio ??v differential input mode [38] hysteresis disabled sio_ref + 0.2 ? ? v v il input voltage low threshold gpio mode cmos input ? ? 0.3 ?? v ddio v differential input mode [38] hysteresis disabled ? ? sio_ref ? 0.2 v v oh output voltage high unregulated mode i oh = 4 ma, v ddio = 3.3 v v ddio ? 0.4 ? ? v regulated mode [38] i oh = 1 ma sio_ref ? 0.65 ? sio_ref + 0.2 v regulated mode [38] i oh = 0.1 ma sio_ref ? 0.3 ? sio_ref + 0.2 v v ol output voltage low v ddio = 3.30 v, i ol = 25 ma ? ? 0.8 v v ddio = 1.80 v, i ol = 4 ma ? ? 0.4 v rpullup pull-up resistor 3.5 5.6 8.5 k ? rpulldown pull-down resistor 3.5 5.6 8.5 k ? i il input leakage current (absolute value) [39] ???? v ih < vddsio 25 c, vddsio = 3.0 v, v ih = 3.0 v ? ? 14 na v ih > vddsio 25 c, vddsio = 0 v, v ih = 3.0 v ? ? 10 a c in input capacitance [39] ??7pf v h input voltage hysteresis (schmitt-trigger) [39] single ended mode (gpio mode) ? 40 ? mv differential mode ? 35 ? mv idiode current through protection diode to v ssio ??100a
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 78 of 131 figure 11-16. sio output high voltage and current, unregulated mode figure 11-17. sio output low voltage and current, unregulated mode figure 11-18. sio output high voltage and current, regulat- ed mode table 11-12. sio ac specifications parameter description conditions min typ max units trisef rise time in fast strong mode (90/10%) [39] cload = 25 pf, v ddio = 3.3 v ? ? 12 ns tfallf fall time in fast strong mode (90/10%) [39] cload = 25 pf, v ddio = 3.3 v ? ? 12 ns trises rise time in slow strong mode (90/10%) [39] cload = 25 pf, v ddio = 3.0 v ? ? 75 ns tfalls fall time in slow strong mode (90/10%) [39] cload = 25 pf, v ddio = 3.0 v ? ? 60 ns
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 79 of 131 figure 11-19. sio output rise and fall times, fast strong mode, v ddio = 3.3 v, 25 pf load figure 11-20. sio output rise and fall times, slow strong mode, v ddio = 3.3 v, 25 pf load fsioout sio output operating frequency 2.7 v < v ddio < 5.5 v, unregu- lated output (gpi o) mode, fast strong drive mode 90/10% v ddio into 25 pf ? ? 33 mhz 1.71 v < v ddio < 2.7 v, unregu- lated output (gpi o) mode, fast strong drive mode 90/10% v ddio into 25 pf ? ? 16 mhz 3.3 v < v ddio < 5.5 v, unregu- lated output (gpio) mode, slow strong drive mode 90/10% v ddio into 25 pf ? ? 5 mhz 1.71 v < v ddio < 3.3 v, unregu- lated output (gpio) mode, slow strong drive mode 90/10% v ddio into 25 pf ? ? 4 mhz 2.7 v < v ddio < 5.5 v, regulated output mode, fast strong drive mode output continuously switching into 25 pf ??20mhz 1.71 v < v ddio < 2.7 v, regulated output mode, fast strong drive mode output continuously switching into 25 pf ??10mhz 1.71 v < v ddio < 5.5 v, regulated output mode, slow strong drive mode output continuously switching into 25 pf ??2.5mhz fsioin sio input operating frequency 1.71 v < v ddio < 5.5 v 90/10% v ddio ??66mhz table 11-12. sio ac specifications (continued) parameter description conditions min typ max units
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 80 of 131 11.4.3 usbio for operation in gpio mode, the standard range for v ddd applies, see device level specifications on page 68. figure 11-21. usbio output high voltage and current, gpio mode figure 11-22. usbio output low voltage and current, gpio mode table 11-13. usbio dc specifications parameter description conditions min typ max units rusbi usb d+ pull-up resistance with idle bus 0.900 ? 1.575 k ? rusba usb d+ pull-up resistance while receiving traffic 1.425 ? 3.090 k ? vohusb static output high 15 k ? 5% to vss, internal pull-up enabled 2.8 ? 3.6 v volusb static output low 15 k ? 5% to vss, internal pull-up enabled ??0.3v vihgpio input voltage high, gpio mode v ddd ?? 3v 2 ? ? v vilgpio input voltage low, gpio mode v ddd ?? 3v ? ? 0.8 v vohgpio output voltage high, gpio mode i oh = 4 ma, v ddd ? 3v 2.4 ? ? v volgpio output voltage low, gpio mode i ol = 4 ma, v ddd ? 3v ? ? 0.3 v vdi differential input sensitivity |(d+)?(d?)| ? ? 0.2 v vcm differential input common mode range ?0.8?2.5v vse single ended receiver threshold ? 0.8 ? 2 v rps2 ps/2 pull-up resistance in ps/2 mode, with ps/2 pull-up enabled 3?7k ? rext external usb series resistor in series with each usb pin 21.78 (?1%) 22 22.22 (+1%) ? zo usb driver output impedance including rext 28 ? 44 ? c in usb transceiver input capacitance ? ? 20 pf i il [40] input leakage current (absolute value) 25 c, v ddd = 3.0 v ? ? 2 na note 40. based on device characterizati on (not production tested).
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 81 of 131 figure 11-23. usbio output rise and fall times, gpio mode, v ddd = 3.3 v, 25 pf load table 11-14. usbio ac specifications parameter description conditions min typ max units tdrate full-speed data rate average bit rate 12 ? 0.25% 12 12 + 0.25% mhz tjr1 receiver data jitter tolerance to next transition ?8 ? 8 ns tjr2 receiver data jitter tolerance to pair transition ?5 ? 5 ns tdj1 driver differential jitter to next transition ?3.5 ? 3.5 ns tdj2 driver differential jitter to pair transition ?4 ? 4 ns tfdeop source jitter for differential transition to se0 transition ?2 ? 5 ns tfeopt source se0 interval of eop 160 ? 175 ns tfeopr receiver se0 interval of eop 82 ? ? ns tfst width of se0 interval durin g differential transition ? ? 14 ns fgpio_out gpio mode output operating frequency 3 v ? v ddd ? 5.5 v ? ? 20 mhz v ddd = 1.71 v ? ? 6 mhz tr_gpio rise time, gpio mode, 10%/90% v ddd v ddd > 3 v, 25 pf load ? ? 12 ns v ddd = 1.71 v, 25 pf load ? ? 40 ns tf_gpio fall time, gpio mode, 90%/10% v ddd v ddd > 3 v, 25 pf load ? ? 12 ns v ddd = 1.71 v, 25 pf load ? ? 40 ns table 11-15. usb driver ac specifications parameter description conditions min typ max units tr transition rise time ? ? 20 ns tf transition fall time ? ? 20 ns tr rise/fall time matching v usb_5 , v usb_3.3 , see usb dc specifications on page 101 90% ? 111% vcrs output signal crossover voltage 1.3 ? 2 v
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 82 of 131 11.4.4 xres 11.5 analog peripherals specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.5.1 opamp note 41. based on device characterizati on (not production tested). table 11-16. xres dc specifications parameter description conditions min typ max units v ih input voltage high threshold 0.7 ? v ddio ??v v il input voltage low threshold ? ? 0.3 ?? v ddio v rpullup pull-up resistor 3.5 5.6 8.5 k ? c in input capacitance [41] ?3?pf v h input voltage hysteresis (schmitt?trigger) [41] ?100?mv idiode current through protection diode to v ddio and v ssio ??100a table 11-17. xres ac specifications parameter description conditions min typ max units t reset reset pulse width 1 ? ? s table 11-18. opamp dc specifications parameter description conditions min typ max units v ioff input offset voltage ? ? 2 mv v os input offset voltage ? ? 2.5 mv operating temperature ?40 c to 70 c ??2mv tcv os input offset voltage drift with temperature power mode = high ? ? 30 v ? / ? c ge1 gain error, unity gain buffer mode rload = 1 k ? ??0.1% c in input capacitance routing from pin ? ? 18 pf v o output voltage range 1 ma, source or sink, power mode = high v ssa + 0.05 ? v dda ? 0.05 v i out output current capability, source or sink v ssa + 500 mv ?? vout ? v dda ?500 mv, v dda > 2.7 v 25 ? ? ma v ssa + 500 mv ? vout ? v dda ?500 mv, 1.7 v = v dda ? 2.7 v 16 ? ? ma i dd quiescent current power mode = min ? 200 270 ua power mode = low ? 250 400 ua power mode = med ? 330 950 ua power mode = high ? 1000 2500 ua cmrr common mode reje ction ratio 80 ? ? db psrr power supply rejection ratio v dda ? 2.7 v 85 ? ? db v dda < 2.7 v 70 ? ? db
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 83 of 131 figure 11-24. opamp voffset histogram, 3388 samples/847 parts, 25 c, vdda = 5 v figure 11-25. opamp voffset vs temperature, v dda = 5v figure 11-26. opamp voffset vs vcommon and v dda , 25 c figure 11-27. opamp output voltage vs load current and temperature, high power mode, 25 c, v dda = 2.7 v figure 11-28. opamp operating current vs v dda and power mode
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 84 of 131 figure 11-29. opamp noise vs frequency, power mode = high, v dda = 5v figure 11-30. opamp step response, rising figure 11-31. opamp step response, falling table 11-19. opamp ac specifications parameter description conditions min typ max units gbw gain-bandwidth product power mode = minimum, 15 pf load 1 ? ? mhz power mode = low, 15 pf load 2 ? ? mhz power mode = medium, 200 pf load 1 ? ? mhz power mode = high, 200 pf load 3 ? ? mhz sr slew rate, 20% - 80% power mode = low, 15 pf load 1.1 ? ? v/s power mode = medium, 200 pf load 0.9 ? ? v/s power mode = high, 200 pf load 3 ? ? v/s e n input noise density power mode = high, v dda = 5 v, at 100 khz ?45?nv/sqrthz note 42. based on device characterizati on (not production tested).
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 85 of 131 11.5.2 delta-sigma adc unless otherwise specified, operating conditions are: ? operation in continuous sample mode ? fclk = 6.144 mhz ? reference = 1.024 v internal reference bypassed on p3.2 or p0.3 ? unless otherwise specified, all ch arts and graphs show typical values table 11-20. 12-bit delta-sigma adc dc specifications parameter description conditions min typ max units resolution 8 ? 12 bits number of channels, single ended ? ? no. of gpio ? number of channels, differential differential pair is formed using a pair of gpios. ?? no. of gpio/2 ? monotonic yes ? ? ? ? ge gain error buffered, buffer gain = 1, range = 1.024 v, 25 c ??0.2% gd gain drift buffered, buffer gain = 1, range = 1.024 v ? ? 50 ppm/c vos input offset voltage buffered, 12-bit mode, v dda = 2.7 v, 25 c ??0.1mv tcvos temperature coefficient, input offset voltage buffer gain = 1, 12-bit, range = 1.024 v ? ? 0.55 v/c input voltage range, single ended [43] v ssa ?v dda v input voltage range, differential unbuf- fered [43] v ssa ?v dda v input voltage range, differential, buffered [43] v ssa ?v dda ? 1 v inl12 integral non linearity [43] range = 1.024 v, unbuffered ? ? 1 lsb dnl12 differential non linearity [43] range = 1.024 v, unbuffered ? ? 1 lsb inl8 integral non linearity [43] range = 1.024 v, unbuffered ? ? 1 lsb dnl8 differential non linearity [43] range = 1.024 v, unbuffered ? ? 1 lsb rin_buff adc input resistance input buffer used 10 ? ? m ? rin_adc12 adc input resistance input buffer bypassed, 12 bit, range = 1.024 v ?148 [44] ?k ? vextref adc external reference input voltage, see also internal reference in voltage reference on page 87 pins p0[3], p3[2] 0.9 ? 1.3 v current consumption i dd_12 current consumption, 12 bit [43] 192 ksps, unbuffered ? ? 1.4 ma i buff buffer current consumption [43] ?? 2.5ma notes 43. based on device characterization (not production tested). 44. by using switched capacitors at the adc in put an effective input resistance is crea ted. holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. this va lue is calculated, not measured. for more information see the technical reference ma nual.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 86 of 131 table 11-21. delta-sigma adc ac specifications parameter description conditions min typ max units startup time ?? 4 samples thd total harmonic distortion [45] buffer gain = 1, 12-bit, range = 1.024 v ? ? 0.0032 % 12-bit resolution mode sr12 sample rate, continuous, high power [45] range = 1.024 v, unbuffered 4 ? 192 ksps bw12 input bandwidth at max sample rate [45] range = 1.024 v, unbuffered ? 44 ? khz sinad12int signal to noise ratio, 12-bit, internal reference [45] range = 1.024 v, unbuffered 66 ? ? db 8-bit resolution mode sr8 sample rate, continuous, high power [45] range = 1.024 v, unbuffered 8 ? 384 ksps bw8 input bandwidth at max sample rate [45] range = 1.024 v, unbuffered ? 88 ? khz sinad8int signal to noise ratio, 8-bit, internal reference [45] range = 1.024 v, unbuffered 43 ? ? db table 11-22. delta-sigma adc sample rates, range = 1.024 v resolution, bits continuous multi-sample min max min max 8 8000 384000 1911 91701 9 6400 307200 1543 74024 10 5566 267130 1348 64673 11 4741 227555 1154 55351 12 4000 192000 978 46900 note 45. based on device characterizati on (not production tested). figure 11-32. delta-sigma adc i dd vs sps, range = 1.024 v, continuous sample mode, input buffer bypassed
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 87 of 131 11.5.3 voltage reference figure 11-33. voltage reference vs. temperature and v cca figure 11-34. voltage reference long-term drift 11.5.4 analog globals table 11-23. voltage reference specifications see also adc external reference specifications in section 11.5.2 . parameter description conditions min typ max units v ref precision reference voltage initial trimming 1.023 (?0.1%) 1.024 1.025 (+0.1%) v temperature drift [46] ?20 c to 80 c, packages 100-tqfp, 68-qfn, 48-qfn ? ? 20 ppm/c ?20 c to 80 c, package 48-ssop ??25 ?40 c to 85 c, packages 100-tqfp, 68-qfn, 48-qfn ??25 ?40 c to 85 c, package 48-ssop ??30 long term drift ? 100 ? ppm/khr thermal cycling drift (stability) [46, 47] ?100 ? ppm table 11-24. analog globals specifications parameter description conditions min typ max units rppag resistance pin-to-pin through p2[4], agl0, dsm inp, agl1, p2[5] [48] v dda = 3 v ? 1472 2200 ? rppmuxbus resistance pin-to-pin through p2[3], amuxbusl, p2[4] [48] v dda = 3 v ? 706 1100 ? notes 46. based on device characterization (not production tested). 47. after eight full cycles between ?40 c and 100 c. 48. the resistance of the analog global and analog mux bus is high if v dda ?? 2.7 v, and the chip is in either sleep or hibernate mode. use of analog global and analog mux bus under these conditions is not recommended. 49. the recommended procedure for using a custom trim va lue for the on-chip comparators can be found in the trm.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 88 of 131 11.5.5 comparator 11.5.6 current digital-to-analog converter (idac) all specifications are based on use of t he low-resistance idac output pins (see pin descriptions on page 10 for details). see the idac component data sheet in psoc creator for fu ll electrical specifications and apis. unless otherwise specified, all charts and graphs show typical values. table 11-25. comparator dc specifications parameter description conditions min typ max units v os input offset voltage in fast mode factory trim, v dda > 2.7 v, vin ? 0.5 v ?10mv input offset voltage in slow mode factory trim, vin ? 0.5 v ? 9 mv input offset voltage in fast mode [48] custom trim ? ? 4 mv input offset voltage in slow mode [48] custom trim ? ? 4 mv input offset voltage in ultra low-power mode v dda 4.6 v ? 12 ? mv v hyst hysteresis hysteresis enable mode ? 10 32 mv v icm input common mode voltage high current / fast mode v ssa ?v dda v low current / slow mode v ssa ?v dda v ultra low power mode v dda 4.6 v v ssa ?v dda ? 1.15 v cmrr common mode rejection ratio ? 50 ? db i cmp high current mode/fast mode [46] ?? 400 a low current mode/slow mode [46] ?? 100 a ultra low-power mode [46] v dda 4.6 v ? 6 ? a table 11-26. comparator ac specifications parameter description conditions min typ max units t resp response time, high current mode [46] 50 mv overdrive, measured pin-to-pin ? 75 110 ns response time, low current mode [46] 50 mv overdrive, measured pin-to-pin ? 155 200 ns response time, ultra low-power mode [46] 50 mv overdrive, measured pin-to-pin, v dda 4.6 v ?55 ? s table 11-27. idac dc specifications parameter description conditions min typ max units resolution ? ? 8 bits i out output current at code = 255 range = 2.04 ma, code = 255, v dda ? 2.7 v, rload = 600 ? ? ?2.04 ? ma range = 2.04 ma, high speed mode, code = 255, v dda ? 2.7 v, rload = 300 ? ?2.04 ? ma range = 255 a, code = 255, rload = 600 ? ?255 ? a range = 31.875 a, code = 255, rload = 600 ? ? 31.875 ? a monotonicity ? ? yes ezs zero scale error ? 0 1 lsb eg gain error range = 2.04 ma, 25 c ? ? 2.5 % range = 255 a, 25 c ? ? 2.5 % range = 31.875 a, 25 c ? ? 3.5 %
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 89 of 131 tc_eg temperature coefficient of gain error range = 2.04 ma ? ? 0.04 % / c range = 255 a ? ? 0.04 % / c range = 31.875 a ? ? 0.05 % / c inl integral nonlinearity sink mode, range = 255 a, codes 8 ? 255, rload = 2.4 k ? , cload = 15 pf ?0.91 lsb source mode, range = 255 a, codes 8 ? 255, rload = 2.4 k ? , cload = 15 pf ?1.21.5 lsb dnl differential nonlinearity sink mode, range = 255 a, rload = 2.4 k ? , cload = 15 pf ?0.31 lsb source mode, range = 255 a, rload = 2.4 k ? , cload = 15 pf ?0.31 lsb vcompliance dropout voltage, source or sink mode voltage headroom at max current, rload to v dda or rload to v ssa , v diff from v dda 1? ? v i dd operating current, code = 0 low speed mode, source mode, range = 31.875 a ? 44 100 a low speed mode, source mode, range = 255 a, ? 33 100 a low speed mode, source mode, range = 2.04 ma ? 33 100 a low speed mode, sink mode, range = 31.875 a ? 36 100 a low speed mode, sink mode, range = 255 a ? 33 100 a low speed mode, sink mode, range = 2.04 ma ? 33 100 a high speed mode, source mode, range = 31.875 a ? 310 500 a high speed mode, source mode, range = 255 a ? 305 500 a high speed mode, source mode, range = 2.04 ma ? 305 500 a high speed mode, sink mode, range = 31.875 a ? 310 500 a high speed mode, sink mode, range = 255 a ? 300 500 a high speed mode, sink mode, range = 2.04 ma ? 300 500 a table 11-27. idac dc specifications (continued) parameter description conditions min typ max units
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 90 of 131 figure 11-35. idac inl vs input code, range = 255 a, source mode figure 11-36. idac inl vs inpu t code, range = 255 a, sink mode figure 11-37. idac dnl vs input code, range = 255 a, source mode figure 11-38. idac dnl vs inpu t code, range = 255 a, sink mode figure 11-39. idac inl vs temperature, range = 255 a, high speed mode figure 11-40. idac dnl vs temperature, range = 255 a, high speed mode
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 91 of 131 figure 11-41. idac full scal e error vs temperature, range = 255 a, source mode figure 11-42. idac full scale error vs temperature, range = 255 a, sink mode figure 11-43. idac operating current vs temperature, range = 255 a, code = 0, source mode figure 11-44. idac operatin g current vs temperature, range = 255 a, code = 0, sink mode table 11-28. idac ac specifications parameter description conditions min typ max units f dac update rate ? ? 8 msps t settle settling time to 0.5 lsb range = 31.875 a or 255 a, full scale transition, high speed mode, 600 ? 15-pf load ? ? 125 ns current noise range = 255 a, source mode, high speed mode, v dda = 5 v, 10 khz ?340 ?pa/sqrthz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 92 of 131 figure 11-45. idac step response, codes 0x40 - 0xc0, 255 a mode, source mode, high speed mode, v dda = 5 v figure 11-46. idac glitch re sponse, codes 0x7f - 0x80, 255 a mode, source mode, high speed mode, v dda = 5 v figure 11-47. idac psrr vs frequency figur e 11-48. idac current noise, 255 a mode, source mode, high speed mode, v dda = 5 v
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 93 of 131 11.5.7 voltage digital to analog converter (vdac) see the vdac component datasheet in psoc creato r for full electrical specifications and apis. unless otherwise specified, all charts and graphs show typical values. figure 11-49. vdac inl vs input code, 1 v mode fi gure 11-50. vdac dnl vs input code, 1 v mode table 11-29. vdac dc specifications parameter description conditions min typ max units resolution ? 8 ? bits inl1 integral nonlinearity 1 v scale ? 2.1 2.5 lsb dnl1 differential nonlinearity 1 v scale ? 0.3 1 lsb rout output resistance 1 v scale ? 4 ? k ? 4 v scale ? 16 ? k ? v out output voltage range, code = 255 1 v scale ? 1.02 ? v 4 v scale, v dda = 5 v ? 4.08 ? v monotonicity ? ? yes ? v os zero scale error ? 0 0.9 lsb eg gain error 1 v scale ? ? 2.5 % 4 v scale ? ? 2.5 % tc_eg temperature coefficient, gain error 1 v scale ? ? 0.03 %fsr / c 4 v scale ? ? 0.03 %fsr / c i dd operating current low speed mode ? ? 100 a high speed mode ? ? 500 a
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 94 of 131 figure 11-51. vdac inl vs temperature, 1 v mode fi gure 11-52. vdac dnl vs temperature, 1 v mode figure 11-53. vdac full scal e error vs temperature, 1 v mode figure 11-54. vdac full scal e error vs temperature, 4 v mode figure 11-55. vdac operating cu rrent vs temperature, 1v mode, low speed mode figure 11-56. vdac operating current vs temperature, 1 v mode, high speed mode
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 95 of 131 figure 11-57. vdac step response, codes 0x40 - 0xc0, 1 v mode, high speed mode, v dda = 5 v figure 11-58. vdac glitch resp onse, codes 0x7f - 0x80, 1 v mode, high speed mode, v dda = 5 v figure 11-59. vdac psrr vs frequency figure 11-60. vdac voltage noise, 1 v mode, high speed mode, v dda = 5 v table 11-30. vdac ac specifications parameter description conditions min typ max units f dac update rate 1 v scale ? ? 1000 ksps 4 v scale ? ? 250 ksps tsettlep settling time to 0.1%, step 25% to 75% 1 v scale, cload = 15 pf ? 0.45 1 s 4 v scale, cload = 15 pf ? 0.8 3.2 s tsettlen settling time to 0.1%, step 75% to 25% 1 v scale, cload = 15 pf ? 0.45 1 s 4 v scale, cload = 15 pf ? 0.7 3 s voltage noise range = 1 v, high speed mode, v dda = 5 v, 10 khz ?750 ?nv/sqrthz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 96 of 131 11.5.8 mixer the mixer is created using a sc/ct analog block; see the mixer co mponent data sheet in psoc creator for full electrical specifi cations and apis. 11.5.9 transimpedance amplifier the tia is created using a sc/ct analog blo ck; see the tia component data sheet in pso c creator for full electrical specificati ons and apis. table 11-31. mixe r dc specifications parameter description conditions min typ max units v os input offset voltage ? ? 10 mv quiescent current ? 0.9 2 ma g gain ? 0 ? db table 11-32. mixe r ac specifications parameter description conditions min typ max units f lo local oscillator frequency down mixer mode ? ? 4 mhz f in input signal frequency down mixer mode ? ? 14 mhz f lo local oscillator frequency up mixer mode ? ? 1 mhz f in input signal frequency up mixer mode ? ? 1 mhz sr slew rate 3 ? ? v/s table 11-33. transimpedance amplifier (tia) dc specifications parameter description conditions min typ max units v ioff input offset voltage ? ? 10 mv rconv conversion resistance [51] r = 20k; 40 pf load ?25 ? +35 % r = 30k; 40 pf load ?25 ? +35 % r = 40k; 40 pf load ?25 ? +35 % r = 80k; 40 pf load ?25 ? +35 % r = 120k; 40 pf load ?25 ? +35 % r = 250k; 40 pf load ?25 ? +35 % r= 500k; 40 pf load ?25 ? +35 % r = 1m; 40 pf load ?25 ? +35 % quiescent current ? 1.1 2 ma table 11-34. transimpedance amplifier (tia) ac specifications parameter description conditions min typ max units bw input bandwidth (?3 db) r = 20k; ?40 pf load 1500 ? ? khz r = 120k; ?40 pf load 240 ? ? khz r = 1m; ?40 pf load 25 ? ? khz notes 50. based on device characteri zation (not production tested). 51. conversion resistance values are not calibrated. calibrated values and deta ils about calibration are provided in psoc creato r component data sheets. external precision resistors can also be used.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 97 of 131 11.5.10 programmable gain amplifier the pga is created using a sc/ct analog block; see the pga compon ent data sheet in psoc creator for full electrical specificati ons and apis. unless otherwise specified, operating conditions are: ? operating temperature = 25 c for typical values ? unless otherwise specified, all ch arts and graphs show typical values figure 11-61. pga voffset histogram, 4096 samples/ 1024 parts table 11-35. pga dc specifications parameter description conditions min typ max units vin input voltage range power mode = minimum v ssa ?v dda v vos input offset voltage power mode = high, gain = 1 ??10mv tcvos input offset voltage drift with temperature power mode = high, gain = 1 ??30v / c ge1 gain error, gain = 1 ? ? 0.15 % ge16 gain error, gain = 16 ? ? 2.5 % ge50 gain error, gain = 50 ? ? 5 % vonl dc output nonlinearity gain = 1 ? ? 0.01 % of fsr cin input capacitance ? ? 7 pf voh output voltage swing power mode = high, gain = 1, rload = 100 k ? to v dda / 2 v dda ? 0.15 ? ? v vol output voltage swing power mode = high, gain = 1, rload = 100 k ? to v dda / 2 ??v ssa + 0.15 v vsrc output voltage under load iload = 250 a, v dda ? 2.7 v, power mode = high ? ? 300 mv idd operating current power mode = high ? 1.5 1.65 ma psrr power supply rejection ratio 48 ? ? db
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 98 of 131 figure 11-62. bandwidth vs. temperature, at different gain settings, power mode = high figure 11-63. noise vs. frequency, v dda = 5 v, power mode = high 11.5.11 temperature sensor 11.5.12 lcd direct drive table 11-36. pga ac specifications parameter description conditions min typ max units bw1 ?3 db bandwidth power mode = high, gain = 1, input = 100 mv peak-to-peak 6.7 8 ? mhz sr1 slew rate power mode = high, gain = 1, 20% to 80% 3?? v/ s e n input noise density p ower mode = high, v dda = 5 v, at 100 khz ?43?nv/sqrthz table 11-37. temperature sensor specifications parameter description conditions min typ max units temp sensor accuracy range: ?40 c to +85 c ? 5 ? c table 11-38. lcd direct drive dc specifications parameter description conditions min typ max units i cc lcd system operating current device sleep mode with wakeup at 400-hz rate to refresh lcds, bus clock = 3 mhz, v ddio = v dda = 3 v, 4 commons, 16 segments, 1/4 duty cycle, 50 hz frame rate, no glass connected ?38 ? ? a i cc_seg current per segment driver strong drive mode ? 260 ? a v bias lcd bias range (v bias refers to the main output voltage(v0) of lcd dac) v dda ? 3 v and v dda ? v bias 2? 5v lcd bias step size v dda ? 3 v and v dda ? v bias ? 9.1 v dda ?mv lcd capacitance per segment/common driver drivers may be combined ? 500 5000 pf long term segment offset ? ? 20 mv i out output drive current per segment driver) v ddio = 5.5v, strong drive mode 355 ? 710 a table 11-39. lcd direct drive ac specifications parameter description conditions min typ max units f lcd lcd frame rate 10 50 150 hz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 99 of 131 11.6 digital peripherals specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.6.1 timer the following specifications apply to the timer/counter/pwm peripheral in timer mo de. timers can also be implemented in udbs; f or more information, see the timer component data sheet in psoc creator. 11.6.2 counter the following specifications apply to the timer/counter/pwm peri pheral, in counter mode. counters can also be implemented in udbs; for more information, see the counter component data sheet in psoc creator. table 11-40. timer dc specifications parameter description conditions min typ max units block current consumption 16-bit timer, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 67 mhz ? 350 ? a table 11-41. timer ac specifications parameter description conditions min typ max units operating frequency dc ? 67.01 mhz capture pulse width (internal) 15 ? ? ns capture pulse width (external) 30 ? ? ns timer resolution 15 ? ? ns enable pulse width 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width 15 ? ? ns reset pulse width (external) 30 ? ? ns table 11-42. counter dc specifications parameter description conditions min typ max units block current consumption 16?bit counter, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 67 mhz ? 350 ? a table 11-43. counter ac specifications parameter description conditions min typ max units operating frequency dc ? 67.01 mhz capture pulse 15 ? ? ns resolution 15 ? ? ns pulse width 15 ? ? ns pulse width (external) 30 ? ? ns enable pulse width 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width 15 ? ? ns reset pulse width (external) 30 ? ? ns
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 100 of 131 11.6.3 pulse width modulation the following specifications apply to the timer/counter/pwm per ipheral, in pwm mode. pwm components can also be implemented in udbs; for more information, see the pwm component data sheet in psoc creator. 11.6.4 i 2 c controller area network [52] table 11-44. pwm dc specifications parameter description conditions min typ max units block current consumption 16-bit pwm, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 67 mhz ? 350 ? a table 11-45. pulse width modulation (pwm) ac specifications parameter description conditions min typ max units operating frequency dc ? 67.01 mhz pulse width 15 ? ? ns pulse width (external) 30 ? ? ns kill pulse width 15 ? ? ns kill pulse width (external) 30 ? ? ns enable pulse width 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width 15 ? ? ns reset pulse width (external) 30 ? ? ns table 11-46. fixed i 2 c dc specifications parameter description conditions min typ max units block current consumption enabled, configured for 100 kbps ? ? 250 a enabled, configured for 400 kbps ? ? 260 a wake from sleep mode ? ? 30 a table 11-47. fixed i 2 c ac specifications parameter description conditions min typ max units bit rate ? ? 1 mbps table 11-48. can dc specifications parameter description conditions min typ max units i dd block current consumption ? ? 200 a note 52. refer to iso 11898 specification for details. table 11-49. can ac specifications parameter description conditions min typ max units bit rate minimum 8 mhz clock ? ? 1 mbit
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 101 of 131 11.6.5 digital filter block 11.6.6 usb table 11-50. dfb dc specifications parameter description conditions min typ max units dfb operating current 64-tap fir at f dfb 100 khz (1.3 ksps) ? 0.03 0.05 ma 500 khz (6.7 ksps) ? 0.16 0.27 ma 1 mhz (13.4 ksps) ? 0.33 0.53 ma 10 mhz (134 ksps) ? 3.3 5.3 ma 48 mhz (644 ksps) ? 15.7 25.5 ma 67 mhz (900 ksps) ? 21.8 35.6 ma table 11-51. dfb ac specifications parameter description conditions min typ max units f dfb dfb operating frequency dc ? 67.01 mhz note 53. rise/fall time matching (tr) not guaranteed, see usb driver ac specifications on page 81. table 11-52. usb dc specifications parameter description conditions min typ max units v usb_5 device supply for usb operation usb configured, usb regulator enabled 4.35 ? 5.25 v v usb_3.3 usb configured, usb regulator bypassed 3.15 ? 3.6 v v usb_3 usb configured, usb regulator bypassed [53] 2.85 ? 3.6 v i usb_configured device supply current in device active mode, bus clock and imo = 24 mhz v ddd = 5 v, f cpu = 1.5 mhz ? 10 ? ma v ddd = 3.3 v, f cpu = 1.5 mhz ? 8 ? ma i usb_suspended device supply current in device sleep mode v ddd = 5 v, connected to usb host, picu configured to wake on usb resume signal ?0.5 ? ma v ddd = 5 v, disconnected from usb host ?0.3 ? ma v ddd = 3.3 v, connected to usb host, picu configured to wake on usb resume signal ?0.5 ? ma v ddd = 3.3 v, disconnected from usb host ?0.3 ? ma
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 102 of 131 11.6.7 universal digital blocks (udbs) psoc creator provides a library of prebuilt and tested standard digital peripherals (uart, spi, lin, prs, crc, timer, counter, pwm, and, or, and so on) that are mapped to the udb array. see the component data sheets in psoc creat or for full ac/dc specificatio ns, apis, and example code. figure 11-64. clock to output performance table 11-53. udb ac specifications parameter description conditions min typ max units datapath performance f max_timer maximum frequency of 16-bit timer in a udb pair ??67.01mhz f max_adder maximum frequency of 16-bit adder in a udb pair ??67.01mhz f max_crc maximum frequency of 16-bit crc/prs in a udb pair ??67.01mhz pld performance f max_pld maximum frequency of a two-pass pld function in a udb pair ??67.01mhz clock to output performance t clk_out propagation delay for clock in to data out, see figure 11-64 . 25 c, v ddd ? 2.7 v ? 20 25 ns t clk_out propagation delay for clock in to data out, see figure 11-64 . worst-case placement, routing, and pin selection ? ? 55 ns
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 103 of 131 11.7 memory specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.7.1 flash 11.7.2 eeprom note 54. see application note an62391 for a description of a low-overhead method of programming psoc 3 flash. table 11-54. flash dc specifications parameter description conditions min typ max units erase and program voltage v ddd pin 1.71 ? 5.5 v table 11-55. flash ac specifications parameter description conditions min typ max units t write row write time (erase + program) ? 15 20 ms t erase row erase time ? 10 13 ms row program time ? 5 7 ms t bulk bulk erase time (16 kb to 64 kb) ? ? 35 ms sector erase time (8 kb to 16 kb) ? ? 15 ms t prog total device programming time no overhead [54] ? 1.5 2 seconds flash data retention time, retention period measured from last erase cycle average ambient temp. t a ? 55 c, 100 k erase/program cycles 20 ? ? years average ambient temp. t a ? 85 c, 10 k erase/program cycles 10 ? ? table 11-56. eeprom dc specifications parameter description conditions min typ max units erase and program voltage 1.71 ? 5.5 v table 11-57. eeprom ac specifications parameter description conditions min typ max units t write single row erase/wr ite cycle time ? 2 20 ms eeprom data retenti on time, retention period measured from last erase cycle average ambient temp, t a ? 25 c, 1m erase/program cycles 20 ? ? years average ambient temp, t a ? 55 c, 100 k erase/program cycles 20 ? ? average ambient temp. t a ? 85 c, 10 k erase/program cycles 10 ? ?
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 104 of 131 11.7.3 nonvolatile latches (nvl)) 11.7.4 sram table 11-58. nvl dc specifications parameter description conditions min typ max units erase and program voltage v ddd pin 1.71 ? 5.5 v table 11-59. nvl ac specifications parameter description conditions min typ max units nvl endurance programmed at 25 c 1k ? ? program/ erase cycles programmed at 0 c to 70 c 100 ? ? program/ erase cycles nvl data retention time programmed at 25 c 20 ? ? years programmed at 0 c to 70 c 20 ? ? years table 11-60. sram dc specifications parameter description conditions min typ max units v sram sram retention voltage 1.2 ? ? v table 11-61. sram ac specifications parameter description conditions min typ max units f sram sram operating frequency dc ? 67.01 mhz
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 105 of 131 11.7.5 external memory interface figure 11-65. asynchronous read cycle timing note 55. limited by gpio output frequency, see table 11-10 on page 76. em_ addr em_ cen em_ oen em_ data em_ wen address data tcel taddrv taddrh toel tdoesu tdoeh table 11-62. asynchronous read cycle specifications parameter description conditions min typ max units t emif clock period [55] v dda ? 3.3 v 30.3 ? ? ns tcel em_cen low time 2t ? 5 ? 2t+ 5 ns taddrv em_cen low to em_addr valid ? ? 5 ns taddrh address hold time after em_wen high t ? ? ns toel em_oen low time 2t ? 5 ? 2t + 5 ns tdoesu data to em_oen high setup time t + 15 ? ? ns tdoeh data hold time after em_oen high 3 ? ? ns
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 106 of 131 figure 11-66. asynchronous write cycle timing table 11-63. asynchronous write cycle specifications parameter description conditions min typ max units t emif clock period [56] v dda ?? 3.3 v 30.3 ? ? ns tc e l em_cen low time t ? 5 ? t + 5 ns taddrv em_cen low to em_addr valid ? ? 5 ns taddrh address hold time after em_wen high t ? ? ns twel em_wen low time t ? 5 ? t + 5 ns tdcev em_cen low to data valid ? ? 7 ns tdweh data hold time after em_wen high t ? ? ns address taddrh tcel taddrv em_ addr em_cen em_ wen em_ oen em_ data twel tdcev tdweh data note 56. limited by gpio output frequency, see table 11-10 on page 76.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 107 of 131 figure 11-67. synchronous read cycle timing table 11-64. synchronous read cycle specifications parameter description conditions min typ max units t emif clock period [57] v dda ?? 3.3 v 30.3 ? ? ns tc p / 2 em_clock pulse high t/2 ? ? ns tc e l d em_cen low to em_clock high 5 ? ? ns tc e h d em_clock high to em_cen high t/2 ? 5 ? ? ns taddrv em_addr valid to em_clock high 5 ? ? ns taddriv em_clock high to em_addr invalid t/2 ? 5 ? ? ns toeld em_oen low to em_clock high 5 ? ? ns toehd em_clock high to em_oen high t ? ? ns tds data valid before em_oen high t + 15 ? ? ns tadscld em_adscn low to em_clock high 5 ? ? ns tadschd em_clock high to em_adscn high t/2 ? 5 ? ? ns em_ addr em_ cen em_ oen em_ data em_ clock address em_ adscn tcp/2 tceld taddrv tcehd taddriv toehd toeld tds tadscld tadschd data note 57. limited by gpio output frequency, see table 11-10 on page 76.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 108 of 131 figure 11-68. synchron ous write cycle timing table 11-65. synchronous write cycle specifications parameter description conditions min typ max units t emif clock period [58] v dda ?? 3.3 v 30.3 ? ? ns tc p / 2 em_clock pulse high t/2 ? ? ns tc e l d em_cen low to em_clock high 5 ? ? ns tc e h d em_clock high to em_cen high t/2 ? 5 ? ? ns taddrv em_addr valid to em_clock high 5 ? ? ns taddriv em_clock high to em_addr invalid t/2 ? 5 ? ? ns tweld em_wen low to em_clock high 5 ? ? ns twehd em_clock high to em_wen high t/2 ? 5 ? ? ns tds data valid before em_clock high 5 ? ? ns tdh data invalid after em_clock high t ? ? ns tadscld em_adscn low to em_clock high 5 ? ? ns tadschd em_clock high to em_adscn high t/2 ? 5 ? ? ns em_ addr em_ cen em_ wen em_ data em_ clock address em_ adscn tcp/2 tceld taddrv tcehd taddriv twehd tweld tds data tadscld tadschd tdh note 58. limited by gpio output frequency, see table 11-10 on page 76.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 109 of 131 11.8 psoc system resources specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.8.1 por with brown out for brown out detect in regulated mode, v ddd and v dda must be ? 2.0 v. brown out detect is not available in externally regulated mode. 11.8.2 voltage monitors table 11-66. precise low-voltage reset (pres) with brown out dc specifications parameter description conditions min typ max units presr rising trip voltage factory trim 1.64 ? 1.68 v presf falling trip voltage 1.62 ? 1.66 v table 11-67. power on reset (p or) with brown ou t ac specifications parameter description conditions min typ max units pres_tr response time ? ? 0.5 s v ddd /v dda droop rate sleep mode ? 5 ? v/sec note 59. based on device characteriza tion (not production tested). table 11-68. voltage monitors dc specifications parameter description conditions min typ max units lvi trip voltage ? ? ? ? lvi_a/d_sel[3:0] = 0000b 1.68 1.73 1.77 v lvi_a/d_sel[3:0] = 0001b 1.89 1.95 2.01 v lvi_a/d_sel[3:0] = 0010b 2.14 2.20 2.27 v lvi_a/d_sel[3:0] = 0011b 2.38 2.45 2.53 v lvi_a/d_sel[3:0] = 0100b 2.62 2.71 2.79 v lvi_a/d_sel[3:0] = 0101b 2.87 2.95 3.04 v lvi_a/d_sel[3:0] = 0110b 3.11 3.21 3.31 v lvi_a/d_sel[3:0] = 0111b 3.35 3.46 3.56 v lvi_a/d_sel[3:0] = 1000b 3.59 3.70 3.81 v lvi_a/d_sel[3:0] = 1001b 3.84 3.95 4.07 v lvi_a/d_sel[3:0] = 1010b 4.08 4.20 4.33 v lvi_a/d_sel[3:0] = 1011b 4.32 4.45 4.59 v lvi_a/d_sel[3:0] = 1100b 4.56 4.70 4.84 v lvi_a/d_sel[3:0] = 1101b 4.83 4.98 5.13 v lvi_a/d_sel[3:0] = 1110b 5.05 5.21 5.37 v lvi_a/d_sel[3:0] = 1111b 5.30 5.47 5.63 v hvi trip voltage 5.57 5.75 5.92 v table 11-69. voltage monitors ac specifications parameter description conditions min typ max units response time [59] ?? 1s
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 110 of 131 11.8.3 interrupt controller 11.8.4 jtag interface figure 11-69. jtag interface timing table 11-70. interrupt controller ac specifications parameter description conditions min typ max units delay from interrupt signal input to isr code execution from isr code includes worse case completion of longest instruction div with 6 cycles ? ? 25 tcy cpu table 11-71. jtag interface ac specifications [60] parameter description conditions min typ max units f_tck tck frequency 3.3 v ? v ddd ? 5v ? ? 14 [61] mhz 1.71 v ? v ddd < 3.3 v ? ? 7 [61] mhz t_tdi_setup tdi setup before tck high (t/10) ? 5 ? ? ns t_tms_setup tms setup before tck high t/4 ? ? t_tdi_hold tdi, tms hold after tck high t = 1/f_tck max t/4 ? ? t_tdo_valid tck low to tdo valid t = 1/f_tck max ? ? 2t/5 t_tdo_hold tdo hold after tck high t = 1/f_tck max t/4 ? ? tdi tck t_tdi_setup tdo (1/f_tck) t_tdi_hold t_tdo_valid t_tdo_hold tms t_tms_setup t_tms_hold notes 60. based on device characteriza tion (not production tested). 61. f_tck must also be no more than 1/3 cpu clock frequency.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 111 of 131 11.8.5 swd interface figure 11-70. swd interface timing 11.8.6 swv interface table 11-72. swd interface ac specifications [62] parameter description conditions min typ max units f_swdck swdclk frequency 3.3 v ? v ddd ? 5v ? ? 14 [63] mhz 1.71 v ? v ddd < 3.3 v ? ? 7 [63] mhz 1.71 v ? v ddd < 3.3 v, swd over usbio pins ??5.5 [63] mhz t_swdi_setup swdio input se tup before swdck high t = 1/f_swdck max t/4 ? ? ? t_swdi_hold swdio input hold after swdck high t = 1/f_swdck max t/4 ? ? ? t_swdo_valid swdck high to swdio output t = 1/f_swdck max ? ? 2t/5 ? swdio (psoc input) swdck t_swdi_setup swdio (psoc output) (1/f_swdck) t_swdi_hold t_sw do_valid t_swdo_hold table 11-73. swv interface ac specifications [62] parameter description conditions min typ max units swv mode swv bit rate ? ? 33 mbit notes 62. based on device characterization (not production tested). 63. f_swdck must also be no more than 1/3 cpu clock frequency.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 112 of 131 11.9 clocking specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.9.1 internal main oscillator figure 11-71. imo current vs. frequency note 64. based on device characteri zation (not production tested). table 11-74. imo dc specifications parameter description conditions min typ max units supply current 62.6 mhz ? ? 600 a 48 mhz ? ? 500 a 24 mhz ? usb mode with oscillator locking to usb bus ? ? 500 a 24 mhz ? non usb mode ? ? 300 a 12 mhz ? ? 200 a 6 mhz ? ? 180 a 3 mhz ? ? 150 a table 11-75. imo ac specifications parameter description conditions min typ max units f imo imo frequency stability (with factory trim) 62.6 mhz ?7 ? 7 % 48 mhz ?5 ? 5 % 24 mhz ? non usb mode ?4 ? 4 % 24 mhz ? usb mode with oscillator locking to usb bus ?0.25 ? 0.25 % 12 mhz ?3 ? 3 % 6 mhz ?2 ? 2 % 3 mhz ?1 ? 1 % startup time [65] from enable (during normal system operation) ??13s
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 113 of 131 figure 11-72. imo frequency variation vs. temperature figure 11-73. imo frequency variation vs. v cc jp?p jitter (peak to peak) [65] f = 24 mhz ? 0.9 ? ns f = 3 mhz ? 1.6 ? ns jperiod jitter (long term) [65] f = 24 mhz ? 0.9 ? ns f = 3 mhz ? 12 ? ns table 11-75. imo ac specifications (continued) parameter description conditions min typ max units note 65. based on device characteri zation (not production tested).
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 114 of 131 11.9.2 internal low speed oscillator figure 11-74. ilo frequency variation vs. temperature figure 11-75. ilo frequency variation vs. v dd 11.9.3 mhz external crystal oscillator 11.9.4 khz external crystal oscillator table 11-76. ilo dc specifications parameter description conditions min typ max units i cc operating current f out = 1 khz ? 0.3 1.7 a f out = 33 khz ? 1.0 2.6 a f out = 100 khz ? 1.0 2.6 a leakage current power down mode ? 2.0 15 na table 11-77. ilo ac specifications parameter description conditions min typ max units startup time, all frequencies turbo mode ? ? 2 ms f ilo ilo frequencies (trimmed) 100 khz 45 100 200 khz 1 khz 0.5 1 2 khz ilo frequencies (untrimmed) 100 khz 30 100 300 khz 1 khz 0.3 1 3.5 khz table 11-78. mhzeco ac specifications parameter description conditions min typ max units f crystal frequency range 4 ? 25 mhz table 11-79. khzeco dc specifications [64] parameter description conditions min typ max units i cc operating current low-power mode; cl= 6 pf ? 0.25 1.0 a dl drive level ? ? 1 w
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 115 of 131 11.9.5 external clock reference 11.9.6 phase-locked loop table 11-80. khzeco ac specifications parameter description conditions min typ max units f frequency ? 32.768 ? khz t on startup time high power mode ? 1 ? s table 11-81. external clock reference ac specifications [68] parameter description conditions min typ max units external frequency range 0 ? 33 mhz input duty cycle range measured at v ddio /2 30 50 70 % input edge rate v il to v ih 0.5 ? ? v/ns table 11-82. pll dc specifications parameter description conditions min typ max units i dd pll operating current in = 3 mhz, out = 67 mhz ? 400 ? a in = 3 mhz, out = 24 mhz ? 200 ? a table 11-83. pll ac specifications parameter description conditions min typ max units fpllin pll input frequency [66] 1?48mhz pll intermediate frequency [67] output of prescaler 1 ? 3 mhz fpllout pll output frequency [66] 24 ? 67 mhz lock time at startup ? ? 250 s jperiod-rms jitter (rms) [68] ??250ps notes 66. this specification is guaranteed by testing the pll across the specified range using the imo as the source for the pll. 67. pll input divider, q, must be set so that the input fre quency is divided down to the intermediate frequency range. value for q ranges from 1 to 16. 68. based on device characterization (not production tested).
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 116 of 131 12. ordering information in addition to the features listed in table 12-1 , every cy8c36 device includes: a precision on-chip voltage reference, precision oscillators, flash, ecc, dma, a fixed function i 2 c, 4 kb trace ram, jtag/swd programming and debug, external memory interface, and more. in addition to these features, the flexible udbs and analog subsection support a wide range of peripherals. to assist you in selecting the ideal part, psoc creator makes a part recommend ation after you choose the components required by your applicat ion. all cy8c36 derivatives incorporate device and flash security in user-selectable security levels; see the trm for details. table 12-1. cy8c36 family with single cycle 8051 part number mcu core analog digital i/o [71] package jtag id [72] cpu speed (mhz) flash (kb) sram (kb) eeprom (kb) lcd segment drive adc dac comparator sc/ct analog blocks [69] opamps dfb capsense udbs [70] 16-bit timer/pwm fs usb can 2.0b total i/o gpio sio usbio 32 kb flash cy8c3665axi-010 67 32 4 1 ? 12-bit del-sig 4 4 4 4 ?? 20 4 ?? 70 62 8 0 100-pin tqfp 01e00a069 cy8c3665pvi-008 67 32 4 1 ? 12-bit del-sig 4 4 4 2 ?? 20 4 ?? 29 25 4 0 48-pin ssop 01e008069 cy8c3665axi-016 67 32 4 1 ? 12-bit del-sig 4 4 4 4 ?? 20 4 ? ? 72 62 8 2 100-pin tqfp 01e010069 cy8c3665lti-044 67 32 4 1 ? 12-bit del-sig 4 4 4 4 ?? 20 4 ? ? 48 38 8 2 68-pin qfn 01e02c069 cy8c3665lti-006 67 32 4 1 ? 12-bit del-sig 4 4 4 2 ?? 20 4 ? ? 31 25 4 2 48-pin qfn 01e006069 cy8c3665pvi-007 67 32 4 1 ? 12-bit del-sig 4 4 4 2 ?? 20 4 ? ? 31 25 4 2 48-pin ssop 01e007069 cy8c3665pvi-080 67 32 4 1 ? 12-bit del-sig 4 4 4 2 ?? 20 4 ? ? 29 25 4 0 48-pin ssop 01e050069 64 kb flash cy8c3666axi-052 67 64 8 2 ? 12-bit del-sig 4 4 4 4 ?? 24 4 ?? 70 62 8 0 100-pin tqfp 01e034069 CY8C3666AXI-036 67 64 8 2 ? 12-bit del-sig 4 4 4 4 ?? 24 4 ? ? 72 62 8 2 100-pin tqfp 01e024069 cy8c3666lti-027 67 64 8 2 ? 12-bit del-sig 4 4 4 4 ?? 24 4 ? ? 48 38 8 2 68-pin qfn 01e01b069 cy8c3666lti-050 67 64 8 2 ? 12-bit del-sig 4 4 4 2 ?? 24 4 ? ? 31 25 4 2 48-pin qfn 01e032069 cy8c3666axi-037 67 64 8 2 ? 12-bit del-sig 4 4 4 4 ?? 24 4 ? ? 70 62 8 0 100-pin tqfp 01e025069 notes 69. analog blocks support a wide variety of func tionality including tia, pga, and mixers. see the example peripherals on page 41 for more information on how analog blocks can be used. 70. udbs support a wide variety of functionality including spi, lin, uart, timer, counter, pwm, prs, and others. individual func tions may use a fraction of a udb or multiple udbs. multiple functions can share a single udb. see the example peripherals on page 41 for more information on how udbs can be used. 71. the i/o count includes all types of digital i/o: gpio, sio, and the two usb i/o. see the i/o system and routing on page 34 for details on the functionality of each of these types of i/o. 72. the jtag id has three major fields. the most significant nibble (left digit) is the version, followed by a 2 byte part numbe r and a 3 nibble manufacturer id.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 117 of 131 12.1 part numbering conventions psoc 3 devices follow the part numbering convention described here. all fields are single character alphanumeric (0, 1, 2, ?, 9 , a, b, ?, z) unless stated otherwise. cy8cabcdefg-xxx ? a: architecture ? 3: psoc 3 ? 5: psoc 5 ? b: family group within architecture ? 4: cy8c34 family ? 6: cy8c36 family ? 8: cy8c38 family ? c: speed grade ? 4: 48 mhz ? 6: 67 mhz ? d: flash capacity ? 4: 16 kb ? 5: 32 kb ? 6: 64 kb ? ef: package code ? two character alphanumeric ? ax: tqfp ? lt: qfn ? pv: ssop ? g: temperature range ? c: commercial ? i: industrial ? a: automotive ? xxx: peripheral set ? three character numeric ? no meaning is associated with these three characters. all devices in the psoc 3 cy8c36 family comply to rohs-6 spec ifications, demonstrating the commitment by cypress to lead-free products. lead (pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. cy press uses nickel-palladium-gold (nipdau) technology for the majority of leadframe-based packages. a high level review of the cypress pb-free position is available on our website. specific package information is also available . package material declaration data sheets (pmdds) identify all substanc es contained within cypress packages. pmdds also confirm the absence of many banned substances. the info rmation in the pmdds will help cypress cust omers plan for recycling or other ?end of life? requirements. architecture cypress prefix family group within architecture speed grade flash capacity package code temperature range peripheral set 3: psoc 3 6: 67 mhz 6: 64 kb pv: ssop i: industrial example cy8c 3 6 v p 6 6ix x -x 6: cy8c36 family
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 118 of 131 13. packaging table 13-1. package characteristics parameter description conditions min typ max units t a operating ambient temperature ?40 25.00 85 c t j operating junction temperature ?40 ? 100 c t ja package ? ja (48-pin ssop) ? 49 ? c/watt t ja package ? ja (48-pin qfn) ? 14 ? c/watt t ja package ? ja (68-pin qfn) ? 15 ? c/watt t ja package ? ja (100-pin tqfp) ? 34 ? c/watt t jc package ? jc (48-pin ssop) ? 24 ? c/watt t jc package ? jc (48-pin qfn) ? 15 ? c/watt t jc package ? jc (68-pin qfn) ? 13 ? c/watt t jc package ? jc (100-pin tqfp) ? 10 ? c/watt table 13-2. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 48-pin ssop 260 c 30 seconds 48-pin qfn 260 c 30 seconds 68-pin qfn 260 c 30 seconds 100-pin tqfp 260 c 30 seconds table 13-3. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 48-pin ssop msl 3 48-pin qfn msl 3 68-pin qfn msl 3 100-pin tqfp msl 3
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 119 of 131 figure 13-1. 48-pin (300 mil) ssop package outline 51-85061 *e
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 120 of 131 figure 13-2. 48-pin qfn package outline 001- 45616 *d
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 121 of 131 figure 13-3. 68-pin qfn 88 with 0.4 mm pitch package outline (sawn version) figure 13-4. 100-pin tqfp (14 14 1.4 mm) package outline 001-09618 *d 51-85048 *g
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 122 of 131 14. acronyms table 14-1. acronyms us ed in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth can controller area network, a communications protocol cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld pc program counter pcb printed circuit board pga programmable gain amplifier table 14-1. acronyms us ed in this document (continued) acronym description
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 123 of 131 15. reference documents psoc? 3, psoc? 5 architecture trm psoc? 3 registers trm phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise low-voltage reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. soc start of conversion table 14-1. acronyms us ed in this document (continued) acronym description sof start of frame spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset swd serial wire debug, a test protocol swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 14-1. acronyms us ed in this document (continued) acronym description
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 124 of 131 16. document conventions 16.1 units of measure table 16-1. units of measure symbol unit of measure c degrees celsius db decibels ff femtofarads hz hertz kb 1024 bytes kbps kilobits per second khr kilohours khz kilohertz k ? kilohms ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? megaohms msps megasamples per second a microamperes f microfarads h microhenrys s microseconds v microvolts w microwatts ma milliamperes ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ? ohms pf picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrthz square root of hertz vvolts
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 125 of 131 17. revision history description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change ** 2714854 06/04/09 pvkv new data sheet *a 2758970 09/02/09 mkea updated part numbering conventions added section 11.7.5 (emif figures and tables) updated gpio and sio ac specifications updated xres pin description and xdata address map specifications updated dfb and comparator specifications updated phub features section and rtc in sleep mode updated idac and vdac dc a nd analog global specifications updated usbio ac and delta sigma adc specifications updated ppor and voltage monitors dc specifications updated drive mode diagram added 48-qfn information updated other electr ical specifications *b 2824546 12/09/09 mkea updated i2c section to reflect 1 mbps. updated table 11-6 and 11-7 (boost ac and dc specs); also added shottky diode specs. changed current for sleep/hibernate mode to include sio; added footnote to analog global specs. updated figures 1-1, 6-2, 7-14, and 8-1. updated table 6-2 and table 6-3 (hibernate and sleep rows) and power modes section. updated gpio and sio ac specifications. updated gain erro r in idac and vdac specifications. updated description of v dda spec in table 11-1 and removed gpio clamp current parameter. updated number of udbs on page 1. moved filo from ilo dc to ac table. added pcb layout and pcb schematic diagrams. updated fgpioout spec (table 11-9). added duty cycle frequency in pll ac spec table. added note for sleep and hibernate modes and active mode specs in table 11-2. linked url in section 10.3 to psoc creator site. updated ja and jc values in table 13-1. updated single sample mode and fast fir mode sections. updated input resistanc e specification in del-sig adc table. added tio_init parameter. updated pga and ugb ac specs. removed spc adc. updated boost converter section. added section 'sio as comparator'; update d hysteresis spec (differential mode) in table 11-10. updated v bat condition and deleted vstart parameter in table 11-6. added 'bytes' column for tables 4-1 to 4-5. *c 2873322 02/04/10 mkea changed maximum value of ppor_tr to '1'. updated v bias specification. updated pcb schematic. updated figure 8-1 and figure 6-3. updated interrupt vector table, updated sales links. updated jtag and swd specifications. removed jp-p and jperiod from eco ac spec table. added note on sleep timer in table 11-2. updated ilo ac and dc specifications. added resolution parameter in vdac and idac tables. updated i out typical and maximum values. changed temperature sensor range to ?40 c to +85 c. removed latchup specification from table 11-1.
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 126 of 131 *d 2903576 04/01/10 mkea updated vb pin in pcb schematic updated tstartup parameter in ac specifications table added load regulation and line regulation parameters to inductive boost regulator dc specifications table updated i cc parameter in lcd direct drive dc specs table updated i out parameter in lcd direct drive dc specs table updated table 6-2 and table 6-3 added bullets on capsense in page 1; added capsense column in section 12 removed some references to footnote [1] changed inc_rn cycles from 3 to 2 (table 4-1) added footnote in pll ac specification table added pll intermediate frequency row wit h footnote in pll ac specs table added udbs subsection under 11.6 digital peripherals updated figure 2-6 (pcb layout) updated pin descriptions section and modified figures 6-6, 6-8, 6-9 updated lvd in tables 6-2 and 6-3; modified low-power modes bullet in page 1 added note to figures 2-5 and 6-2; updat ed figure 6-2 to add capacitors for v dda and v ddd pins. changed v ref from 0.9 to 0.1% updated boost converter section (6.2.2) updated tstartup values in table 11-3. removed ipor rows from table 11-68. updated 6.3.1.1, power voltage level monitors. updated section 5.2 and table 11-2 to corre ct suggestion of execution from flash. updated v ref specs in table 11-21. updated idac uncompensated gain error in table 11-25. updated delay from interrupt signal in put to isr code execution from isr code in table11- 72. removed other line in table. added sentence to last par agraph of section 6.1.1.3. updated t resp , high and low-power modes, in table 11-24. updated f_tck values in table 11-73 and f_swdck values in table 11-74. updated snr condition in table 11-20. corrected unit of measurement in table 11-21. updated sleep wakeup time in table 6-3 and tsleep in table 11-3. added 1.71 v <= v ddd < 3.3 v, swd over usbio pins value to table 11-74. removed mention of hibernate reset (hre s) from page 1 features, table 6-3, section 6.2.1.4, section 6. 3, and section 6.3.1.1. change ppor/pres to tbds in section 6.3.1.1, sectio n 6.4.1.6 (changed ppor to reset), table 11-3 (changed ppor to pres), table 11-68 (changed title, values tbd), and table 11-69 (changed ppor_tr to pres_tr). added sentence saying that lvd circuits can generate a reset to section 6.3.1.1. changed i dd values on page 1, page 5, and table 11-2. changed resume time value in section 6.2.1.3. changed esd hbm value in table 11-1. changed sample rate row in table 11-20. removed v dda = 1.65 v rows and changed bwag value in table 11-22. changed v ioff values and changed cmrr value in table 11-23. changed inl max value in table 11-27. added max value to the quiescent current specs in tables 11-29 and 11-31. changed occurrences of ?block? to ?row? and deleted the ?ecc not included? footnote in table 11-57. changed max response time value in tables 11-69 and 11-71. changed the startup time in table 11-79. added condition to intermediate frequency row in table 11-85. added row to table 11-69. added brown out note to section 11.8.1. description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 127 of 131 *e 2938381 05/27/10 mkea replaced v ddio with v ddd in usbio diagram and specification tables, added text in usbio section of electrical specifications. added table 13-2 (package msl) modified tstorag condition and changed max spec to 100 added bullet (pass) under alu (section 7.2.2.2) added figures for khzeco and mhzeco in the external oscillator section updated figure 6-1(clocking subsystem diagram) removed cpuclk_div in table 5-2, deleted clock divider sfr subsection updated psoc creator framework image updated sio dc specifications (v ih and v il parameters) updated bullets in clocking system and clocking distribution sections updated figure 8-2 updated pcb layout and schematic, updated as per mtrb review comments updated table 6-3 (power changed to current) in 32khz ec dc specifications table, changed i cc max to 0.25 in imo dc specifications table, updated supply current values updated gpio dc specs table *f 2958674 06/22/10 shea minor ecn to post data sheet to external website *g 2989685 08/04/10 mkea added usbio 22 ohm dp a nd dm resistors to simplified block diagram added to table 6-6 a footnote and references to same. added sentences to the resistive pull-up and pull-down description bullets. added sentence to section 6.4.11, adjustable output level. updated section 5.5 external memory interface updated table 11-73 jtag in terface ac specifications updated table 11-74 swd interface ac specifications updated style changes as per the new template. *h 3078568 11/04/10 mkea updated ?current digital-to-analog converter (idac)? on page 88 updated ?voltage digital to analog converter (vdac)? on page 93 updated ?dc specifications? on page 68 updated ?voltage reference specifications? on page 87 *i 3107314 12/10/2010 mkea updated delta-sigma tables and graphs. updated flash ac specs formatted table 11.2. updated interrupt controller table updated transimpedance amplifier section updated sio dc specs table updated voltage monitors dc specifications table updated lcd direct drive dc specs table replaced the discrete time mixer and c ontinuous time mixer tables with mixer dc and ac specs tables updated esd hbm value. updated idac and vdac sections removed eso parts from ordering information changed usbio pins from nc to dnu and removed redundant usbio pin description notes updated por with brown out dc and ac specs updated pga ac specs updated 32 khz external crystal dc specifications updated opamp ac specs updated xres io specs updated inductive boost regulator section delta sigma adc spec updates updated comparator section removed buzz mode from power mode transition diagram updated opamp dc and ac spec tables updated pga dc table description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 128 of 131 *j 3179219 02/22/2011 mkea updated conditions for flash data retention time. updated 100-pin tqfp package spec. updated eeprom ac specifications. *k 3200146 03/28/2011 mkea removed preliminary status from the data sheet. updated jtag id deleted cin_g1, adc input capacitance from delta-sigma adc dc spec table updated jtag interface ac specificati ons and swd interface specifications tables updated usbio dc specs added 0.01 to max speed updated features on page 1 added section 5.5, nonvolatile latches updated flash ac specs added can dc specs updated delta-sigma graphs, noise histog ram figures and rms noise spec tables add reference to application note an58304 in section 8.1 updated 100-pin tqfp package spec added oscillator, i/o, vdac, regulator graphs updated jtag/swd timing diagrams updated gpio and sio ac specs updated por with brown out ac spec table updated idac graphs added dma timing diagram, interrupt timing and interrupt vector, i2c timing diagrams updated opamp graphs and pga graphs added full chip performance graphs changed mhzeco range. added ?solder reflow peak temperature? table. *l 3259185 05/17/2011 mkea added jtag and swd interface connection diagrams updated t ja and t jc values in table 13-1 changed typ and max values for the tcvos parameter in opamp dc specifications table. updated clocking subsystem diagram. changed vssd to vssb in the psoc power system diagram updated ordering information. description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 129 of 131 *m 3464258 12/14/2011 mkea updated analog global specs updated idac range updated tia section modified vddio description in section 3 added note on sleep and hibernate modes in the power modes section updated boost converter section updated conditions for inductive boost ac specs added vdac/idac noise graphs and specs added pin capacitance specs for eco pins removed c l from 32 khz external crystal dc specs table. added reference to an5443 9 in section 6.1.2.2 deleted t_swdo_hold row from the swd interface ac specifications table removed pin 46 connections in ?example schematic for 100-pin tqfp part with power connections? updated active mode idd description in table 11-2. added i dddr and i ddar specs in table 11-2. replaced ?total device program time? with t prog in flash ac specs table added i gpio , i sio and i usbio specs in absolute maximum ratings added conditions to i cc spec in 32 khz external crystal dc specs table. updated tcv os value removed boost efficiency vs v out graph updated boost graphs updated min value of gpio input edge rate removed 3.4 mbps in udbs from i2c section updated usbio block diagram; added usbio drive mode description updated analog interconnect diagram changed max imo startup time to 12 s added note for i il spec in usbio dc specs table updated gpio block diagram updated voltage reference specs added text explaining power supply ramp up in section 11-4. description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change
psoc ? 3: cy8c36 family data sheet document number: 001-53413 rev. *o page 130 of 131 *n 3645908 06/14/2012 mkea added paragraph clarifying that to achieve low hibernate current, you must limit the frequency of io input signals. revised description of ipor and clarified pres term. changed footnote to state that all gpio input voltages - not just analog voltages - must be less than vddio. updated 100-tqfp package drawing clarified description of opamp iout spec changed ?compliant with i2c? to ?compatible with i2c? updated 48-qfn package drawing changed reset status register description te xt to clarify that not all reset sources are in the register updated example pcb layout figure removed text stating that ftw is a wakeup source changed supply ramp rate spec from 1 v/ns to 0.066 v/s added ?based on char? footnote to voltage monitors response time spec changed analog global spec descriptions and values added spec for esdhbm for when vssa and vssd are separate added a statement about support fo r jtag programmers and file formats changed comparator specs and conditions added text describing flash cache, and updated related text changed text and added figures describing vddio source and sink added a statement about support for jtag programmers and file formats. changed comparator specs and conditions added text on adjustability of buzz frequency updated terminology for ?ma ster? and ?system? clock deleted the text ?debug operations are possible while the device is reset? deleted and updated text regarding sio performance under certain power ramp conditions removed from boost mention of 22 h inductors. this included deleting some graph figures. changed dac high and low speed/power mode descriptions and conditions changed imo startup time spec added text on xres and pres re-arm times added text about usage in externally regulated mode updated package diagram spec 001-45616 to *d revision. changed supply ramp rate spec from 1 v/ns to 0.066 v/s changed text describing sio modes for overvoltage tolerance added chip idd specs for active and low-power modes, for multiple voltage, temperature and usage conditions added chip idd specs for active and low-power modes, for multiple voltage, temperature and usage conditions updated vref temperature drift specs. added vref graphs and footnote. updated dfb description text changed load cap conditions in opamp specs updated del-sig adc spec tables, to replac e three the instances of ?16 bit? with ?12 bit? updated package diagram spec 001-45616 to *d revision *o 3648803 06/18/2012 wka/ mkea no changes. eros update. description title: psoc ? 3: cy8c36 family data sheet programmable system-on-chip (psoc ? ) document number: 001-53413 revision ecn submission date orig. of change description of change
document number: 001-53413 rev. *o revised june 18, 2012 page 131 of 131 capsense ? , psoc ? 3, psoc ? 5, and psoc ? creator? are trademarks and psoc ? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c comp onents from cypress or on e of its sublicensed associ ated companies co nveys a license u nder the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. arm is a registered trademark, and keil, and realview are trademarks, of arm limited. all products and company names mentioned in this document may be the trademarks of their respective holders. psoc ? 3: cy8c36 family data sheet ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation a ssumes no responsib ility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of su ch use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. an y reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 18. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of of fices, solution centers, ma nufacturers? representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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